Clutch: High Performance Vector-Scalar Comparison using DRAM via Chunked Temporal Coding

Abstract: Vector-scalar comparison is a fundamental computation primitive that compares each element in a vector against a single scalar value. It is widely used in various data-intensive workloads from databases to machine learning. Due to its low computational intensity, its execution tends to be memory-bound, limiting the utilization of compute resources. Processing-using-DRAM (PuD) is an emerging computing paradigm that performs massively parallel bitwise operations directly inside DRAM arrays, alleviating off-chip data movement. Existing PuD-based approaches require many DRAM commands because the comparison's algorithmic complexity grows with operand bit-width in the bit-serial execution model. This command overhead becomes the dominant bottleneck, limiting application-level speedup. We propose Clutch, a data representation and comparison algorithm that accelerates vector-scalar comparisons in PuD systems with high efficiency and scalability. Clutch first uses temporal coding, encoding each vector value as a sequence of leading ones, which enables lookup-based comparison against a scalar by accessing the corresponding DRAM row. To avoid the prohibitive memory footprint of lookup tables at high precision, Clutch partitions operands into multiple multi-bit chunks, compares chunks independently using compact lookup tables, and merges the per-chunk results with a PuD-efficient procedure. By adjusting the number of chunks, Clutch provides a flexible tradeoff between throughput and memory usage. Across predicate evaluation and decision tree inference, Clutch improves end-to-end application throughput and energy efficiency by an average of 12x and 69x over highly optimized CPU and GPU execution, and by 2.9x and 3.0x over the state-of-the-art bit-serial PuD implementation. We also present the first mapping of decision tree inference to PuD execution, extending PuD to a new application domain.

• The paper presents Clutch, a chunked temporal coding method that dramatically reduces DRAM PuD commands and enables high-precision vector-scalar comparisons.
• It partitions operands into multi-bit chunks with dedicated lookup tables, then recursively merges results using efficient in-DRAM logic primitives, offering configurable trade-offs.
• Clutch achieves up to 36× throughput over CPU and 83× over bit-serial PuD in applications like GBDT inference and predicate evaluation, highlighting its energy efficiency.

Clutch: High Performance Vector-Scalar Comparison using DRAM via Chunked Temporal Coding

Introduction and Motivation

Vector-scalar comparisons represent a core computation pattern in data-intensive workloads, from predicate evaluation in databases to feature-thresholding in gradient boosting decision tree (GBDT) inference. Although their computational simplicity is appealing, these operations are fundamentally memory-bound: for large vectors, DRAM bandwidth is the inherent bottleneck, stalling CPU- and even GPU-based systems. Processing-using-DRAM (PuD) has emerged as a promising substrate for such operations, offloading computation directly into memory and reducing unnecessary data movement. However, conventional bit-serial PuD approaches require a number of in-memory operations that scales linearly with operand width, quickly saturating their command processing capabilities and stalling throughput.

The paper "Clutch: High Performance Vector-Scalar Comparison using DRAM via Chunked Temporal Coding" (2606.22812) addresses this critical issue by proposing a new algorithm and data representation, Clutch, which brings both high efficiency and programmability to comparison-centric workloads on PuD hardware.

Architecture and Algorithmic Innovations

Clutch's algorithmic foundation consists of two principal ideas: (1) a temporal coding vector representation, and (2) a chunked divide-and-conquer comparison strategy. Temporal coding replaces conventional binary representation by encoding an integer $v$ as a sequence of leading ones followed by trailing zeros. The $i$-th bit directly yields the comparison result for $i < v$, turning the DRAM row layout into a lookup structure indexed by a scalar for simultaneous vector-wise comparisons.

However, realizing high-precision (e.g., 16- or 32-bit) temporal coding in existing DRAM architectures is infeasible due to row budget limitations. Clutch partitions operands into multiple multi-bit chunks, each chunk leveraging its own small lookup table. Comparison results from chunks are recursively merged by an in-DRAM procedure optimized for PuD logic primitives.

Figure 2: Clutch's encoding and chunked algorithm enables efficient lookup and hierarchical merging of comparison results.

The merging logic relies on expressing the overall comparison $a < b$ as the composition of per-chunk comparisons, such that chunk-wise results can be merged purely with AND/OR/MAJ operations, which are efficiently implemented in DRAM via existing primitives.

Throughput, Energy, and Tradeoff Analysis

One of Clutch's main strengths is its configurability: by adjusting chunk size and count, one can flexibly trade memory footprint for throughput. With more/fewer chunks, Clutch can balance DRAM row budget constraints and PuD command count.

Figure 4: The throughput-memory footprint tradeoff for different chunking strategies demonstrates the scalability of Clutch.

Experimental results indicate strong performance and energy efficiency gains across the precision spectrum. For 32-bit comparisons, Clutch reduces the number of PuD commands to less than 20—an order-of-magnitude reduction relative to bit-serial designs. On practical workloads, this yields up to 36$\times$ throughput (20$\times$ on average) over CPU baselines and 4.1$\times$ (3.1$\times$ on average) over bit-serial PuD implementations.

Figure 6: Throughput scaling with bit-precision, where Clutch outperforms CPU and bit-serial PuD, especially at high precision.

Energy analysis reinforces these findings. Clutch delivers up to 96$\times$ (54$\times$ on average) better energy efficiency than highly optimized CPU baselines and up to 4.2$i$0 (3.1$i$1 on average) over bit-serial PuD.

Figure 8: Energy efficiency comparison highlights the superior power-performance benefits of Clutch.

Application Case Studies: GBDT Inference and Predicate Evaluation

Clutch's impact extends to complete applications. In GBDT inference, especially architectures such as CatBoost (which features oblivious tree structures), tree traversal can be reformulated as a series of vector-scalar comparisons. Clutch enables in-DRAM computation of all comparison and masking steps while the host CPU aggregates the final prediction, offering up to 4.5$i$2 speedup compared to ARM Cortex-A53-based systems for common tabular data benchmarks.

Figure 10: Clutch's mapping of GBDT trees and its associated inference flow enable efficient in-DRAM execution.

Figure 12: Execution flow for Clutch-based GBDT inference, illustrating vector-scalar comparison and masking stages.

Application-level sensitivity analyses show that Clutch's advantage grows with feature and input batch size, aligning with the increase of comparison-dominated execution time.

Figure 14: Normalized throughput for GBDT inference across data types and precisions shows consistent Clutch superiority.

A fine-grained breakdown attributes the majority of execution time and energy in legacy PuD and CPU baselines to in-memory comparison steps. Clutch shifts the bottleneck to post-comparison aggregation, demonstrating successful elimination of the memory-compute bottleneck for critical steps.

Figure 1: Breakdown of execution time and energy showing dramatic reductions in in-DRAM computation cost with Clutch.

Memory and conversion overheads are also addressed: when reused over practical batch sizes, data transformation costs are amortized quickly.

Figure 3: Evaluation of conversion overhead and memory footprint, showing rapid amortization of one-time preprocessing costs with Clutch.

In predicate evaluation (e.g., SQL-like WHERE clause processing), Clutch achieves up to 83$i$3 throughput over the CPU and up to 4$i$4 over bit-serial PuD, with similar improvements in energy efficiency.

Figure 5: Throughput scaling for common database queries benchmarks under Clutch shows its application-level robustness.

Optimization of chunk granularity enables operation within a desired memory budget, while still delivering large throughput gains.

Figure 7: Throughput and memory footprint tradeoff for Q2, demonstrating Clutch's adaptability.

On modern CPU and GPU platforms, Clutch achieves up to 81$i$5 and 5.7$i$6 speedup (respectively).

Figure 9: CPU-based system throughput scaling.

Figure 11: GPU-based system throughput scaling.

When non-comparison steps dominate, as in queries with complex post-processing, the end-to-end speedup is naturally limited; Clutch's value is highest when comparisons are the primary bottleneck.

Figure 13: Execution time breakdown for complex queries highlighting the reduced scope for improvement when comparison is not dominant.

Limitations and Practical Considerations

Clutch's benefits are workload and system-dependent. Throughput/energy improvements are limited if (i) the working set fits in cache, (ii) vector data is highly dynamic (limiting amortization of conversion cost), (iii) memory headroom is absent, or (iv) comparison is not the dominant bottleneck. In such cases, falling back to bit-serial PuD, processor-centric, or hybrid execution may be appropriate.

System integration is straightforward: Clutch leverages existing host-driven PuD execution models, requiring only modest controller/ISA extensions. The algorithm does not require NOT operations—optimizing for both modified and unmodified DRAM platforms.

Implications and Future Directions

Clutch's approach underscores the utility of algorithm–architecture codesign, highlighting that the full benefits of in-DRAM processing require data layout and computation rethinking beyond bit-serial protocols. By demonstrating application-level speedups at both the microkernel and macro-workload level, Clutch establishes the viability of DRAM as a high-performance, energy-efficient substrate for comparison-dominated tasks. Future DRAM developments (e.g., increasing column-level and subarray-level parallelism) will likely further amplify these benefits.

Potential research avenues include dynamic-format switching for changing workload characteristics, extending the encoding and merging logic for other non-arithmetic functions, hybrid memory systems blending Clutch and bit-serial PuD, and hardware support for rapid data format conversions.

Conclusion

Clutch advances the state-of-the-art in vector-scalar comparison on PuD systems through its chunked temporal coding and hierarchical merging strategy. It achieves strong throughput and energy-efficiency improvements across representative workloads such as GBDT inference and predicate evaluation, with demonstrated scalability to high bit-precisions and practical row budgets. The work highlights DRAM's potential not merely as a storage or data movement bottleneck, but as an active, high-throughput compute substrate for next-generation comparison-centric computing.