Quantum Thermal Logic Gates

Abstract: We propose a new concept for quantum thermal logic gates -- analogous to classical electronic logic gates -- that exploit the heat current in a coupled quantum-dot system tunnel-coupled to metallic thermal reservoirs for logic operations in quantum circuits. We obtained a remarkable one-to-one correspondence with the structure of classical electronic logic gate circuits. An experimental setup is presented that demonstrates a realizable nano-electronic quantum circuit architecture for implementing such quantum thermal logic operations.

• The paper introduces an innovative quantum thermal logic architecture utilizing CQD junctions to map classical logic using heat currents.
• It employs a Lindblad master equation framework to derive precise analytical solutions and robust operational thresholds.
• Experimental proposals demonstrate energy-efficient, programmable thermal computation for scalable quantum nanoelectronic applications.

Quantum Thermal Logic Gates: Theory, Operation, and Implications

Introduction

"Quantum Thermal Logic Gates" (2606.06432) introduces a novel architecture for thermally driven logical operations in quantum circuit platforms, leveraging heat currents in Coulomb-coupled quantum-dot (CQD) junctions. This paradigm is motivated by the increasing demand for energy-efficient computation and thermal management in nano-electronic devices where quantum effects and local temperature gradients are dominant. The paper establishes rigorous one-to-one mapping with the structure of classical electronic logic gates, achieves robust logic operational thresholds, and proposes a practical experimental nano-circuit architecture. The overarching goal is integrating programmable thermal computation into scalable quantum technologies.

Figure 1: Schematic for CQD-based QTLG, showing logic mapping between input reservoir temperatures and output heat currents; inset depicts energy level structure relevant for diode operation.

General Model and Physical Formalism

The CQD framework consists of two quantum dots ($\rm QD_a$, $\rm QD_b$), capacitively coupled via strong Coulomb interaction ($U$), each tunnel-coupled to multiple metallic reservoirs. Only single levels per dot are thermally accessible, and transport is strictly governed via fermionic excitations and energy exchange. The joint system is described by a Lindblad master equation (LME) capturing open-system quantum stochastic thermodynamics with all relevant transition rates, spectral functions, and Fermi-Dirac statistics.

Heat currents serve as the logic signal: input logic is encoded in the temperature of the source leads (hot $\sim$ 200 mK $\rightarrow$ logic-1, cold $\sim$ 50 mK $\rightarrow$ logic-0), while the measured output is via steady-state heat current at drain or inverter leads, with experimental thresholds ($J_{\rm Q}^{0}\sim65$ aW, $J_{\rm Q}^{1}\sim100$ aW) delineating binary states. The methodology yields precise analytical solutions for cycle rates and current magnitudes.

Logic Gate Implementation

Single-Input Gates

Quantum Thermal Buffer Gate (QTBG) and NOT Gate (QTNG) are realized via thermal-diode configurations under forward-bias:

• Buffer Gate: Heat cycles proceed only under thermodynamically favorable conditions; for input-1 (hot source), the CQD cycle yields measurable heat flow at the drain (output-1); for input-0 (cold source), the cycle is suppressed (output-0).
• NOT Gate: Addition of a high-temperature inverter lead enables output inversion. For input-0, the inverter drives the heat cycle (output-1); for input-1, competing flows null the inverter output (output-0). The operational robustness is confirmed by strong separation ($\sim$ 40 aW difference) between low/high output logic currents.

  Figure 2: QTBG operation and heat-current response versus source temperature; inset shows diode equivalent circuit.

  

  Figure 3: QTNG circuit and output heat-current dependence on source input, with marked logic thresholds.

Double-Input Gates

Logic gates with two source inputs (S1, S2) span OR, AND, NOR, and NAND structures, closely paralleling classical circuit arrangements:

• OR Gate: Parallel thermal-diode configuration; any hot input enables the heat cycle (output-1), otherwise suppressed (output-0).
• AND Gate: Control lead (C) at fixed high temperature enables only joint action of both hot inputs to exceed threshold output current (output-1). Reverse-bias and forward-bias conditions are set for C/D leads to selectively favor desired cycles. Partial heat currents from anti-clockwise cycles remain below the logic threshold, ensuring clean logic separation.
• NOR/NAND Gate: Combination with inverter (I) lead. Only for joint cold inputs does the inverter output exceed threshold (logic-1); otherwise suppressed. For NAND, only dual hot inputs nullify heat-flow at I lead (output-0); otherwise, finite heat current from I (output-1).

All gate types are shown to reproduce strict logic truth tables with calculated current maps as function of input temperatures. Numerical results verify operational fidelity.

Figure 4: Double-input gate layouts and 2D heat-current maps illustrating clear logic boundaries for OR, AND, NOR, and NAND gates.

Experimental Realization

The proposed architecture is directly mapped onto a nano-electronic device structure: CQD junctions integrated with local heaters and thermometry. Source leads receive programmable heating voltages to define input logic; drain, inverter, and control leads are maintained at fixed or base temperatures for output discrimination and logic control. Standard quantum-dot fabrication techniques (e.g., superconducting contacts, gate voltage tuning) suffice. Local thermometers based on proximity-effect junctions yield precise heat-flow readout. All model parameters correspond to experimentally accessible regimes ($\rm QD_b$0 GHz, $\rm QD_b$1 $\rm QD_b$2eV, heat currents $\rm QD_b$3 100 aW).

Figure 5: Schematic of dual-QD device with back-gate tunability and integrated lead heaters/thermometers.

Numerical Results and Operational Thresholds

The paper reports strong numerical separation between output currents for logic-0 and logic-1 in all gates; e.g., buffer/NOT gates achieve $\rm QD_b$4 differences $\rm QD_b$5 aW, robust against weak tunneling and thermal fluctuations. AND/NAND gates utilize controlled biasing of C and I leads to achieve selective amplification or suppression of heat cycles, resulting in operational logic boundaries directly observable in thermal current maps.

Practical and Theoretical Implications

The QTLG paradigm enables:

• Energy-Efficient Quantum Computation: Non-charge-based logic operation eliminates Joule dissipation, targeting circuits where quantum heat transport dominates.
• Programmable Thermal Management: Heat-flow as binary variable allows dynamic in-situ management of device cooling, error correction, and waste-heat harvesting.
• Nanoelectronic Integration: Direct compatibility with quantum-dot networks, cryogenic electronics, and superconducting thermometry.
• Thermodynamic Computation: Facilitates studies of entropy production and quantum stochastic thermodynamics in functional circuit components.

Future developments may extend to quantum-coherent manipulation of heat currents, integration with quantum batteries, quantum refrigerators, and hybrid phononic-electronic computation frameworks. Experimental scalability is limited by local thermometry resolution and device fabrication, but current technology is already sufficient for demonstration.

Conclusion

Quantum thermal logic gates as constructed in this work establish complete binary logic operation via heat currents in CQD junctions, mapped rigorously onto classical circuit architectures. Robust operational thresholds, analytic cycle analysis, and direct device proposals ensure experimental feasibility. The implications for quantum circuit design, energy-efficient computation, and thermodynamic control are profound, providing a versatile platform for both fundamental and applied research in quantum nanoelectronics.