Multi-Qubit Dyadic Phase Fixing for Fault-Tolerant Quantum Compilation

Abstract: Fault-tolerant quantum computing requires translating application-level quantum circuits into the Clifford+$T$ gate set, where the $T$ gate is the dominant resource cost. Phase kickback is an ancilla-based technique that can dramatically reduce $T$-count for rotations with dyadic angles, but has previously been limited to highly structured circuit families. We present Dyadic Phase Fixing (DPF), a general multi-qubit synthesis tool that extends phase kickback to general quantum circuits. DPF uses numerical unitary synthesis to greedily extract dyadic angle rotations from any input circuit. Combined with a decision matrix to automatically size the final phase gradient register, our end-to-end workflow achieves up to 70% reduction in $T$-count compared to \texttt{gridsynth} and up to 60% compared to Repeat-Until-Success synthesis on a diverse set of benchmarks. We map these compiled circuits to a surface-code architecture to evaluate space-time volume, demonstrating up to a 60\% reduction in this metric as well. However, for some circuits and mapping strategies the two metrics diverge significantly, demonstrating that $T$-count alone is a useful but incomplete proxy for fault-tolerant program costs.

• The paper introduces the DPF compiler infrastructure that generalizes phase kickback to arbitrary quantum circuits, achieving resource savings without sacrificing synthesis performance.
• It employs a block-partitioned unitary synthesis strategy using BQSKit-FT to rewrite Rz rotations as dyadic values and optimally trade off ancilla utilization versus T-gate cost.
• Experimental results demonstrate up to 70% T-count reduction and 60% space-time volume savings across benchmarks such as QFT, QAE, and QAOA, highlighting practical hardware-aware benefits.

Multi-Qubit Dyadic Phase Fixing for Fault-Tolerant Quantum Compilation

Introduction and Motivation

The compilation of quantum programs for execution on fault-tolerant quantum computers fundamentally requires translation into discrete gate sets—in practice, Clifford+$T$—where the $T$ gate dominates resource consumption due to the cost of magic state distillation and injection. While the gridsynth algorithm provides optimal ancilla-free Clifford+$T$ synthesis for $R_z$ gates with $O(\log(1/\epsilon))$ $T$-count scaling, techniques such as phase kickback can dramatically reduce $T$-count for rotations with dyadic angles ($\frac{2m\pi}{2^k}$), but prior to this work have remained limited to highly structured and narrow circuit classes.

This paper introduces the Dyadic Phase Fixing (DPF) compiler infrastructure, which generalizes multi-qubit phase kickback synthesis to arbitrary quantum circuits. The workflow greedily rewrites input circuits to maximize the use of dyadic rotations and employs a decision matrix to trade off register size and ancilla utilization versus $T$-gate savings, always guaranteeing performance at least as good as default ancilla-free synthesis.

Dyadic Phase Fixing and Workflow

The Dyadic Phase Fixing algorithm extends the applicability of phase kickback by numerically identifying opportunities to rewrite $R_z$ rotations in arbitrary circuits as dyadic multiples, beyond their native appearance in, e.g., QFTs and amplitude amplification subroutines. This is achieved through a block-partitioned unitary synthesis strategy, leveraging BQSKit-FT numerical optimization to parameterize subcircuits and subsequently "fix" $T$0 angles greedily to dyadic values, up to a user-specified maximum register size.

The complete compilation workflow is structured as follows:

1. Partition the logical circuit into width-$T$1 blocks.
2. For each block, apply BQSKit-FT for continuous rotation reduction while bounding per-block error using the Hilbert-Schmidt metric, distributing the global error $T$2 across blocks.
3. Apply DPF to each block, greedily replacing suitable $T$3 gates with dyadic rotations.
4. Invoke a decision matrix to choose the optimal phase gradient register size, balancing overhead with T-count reduction.
5. For remaining non-dyadic $T$4 gates, revert to gridsynth to complete decomposition to the Clifford+$T$5 set.

   Figure 1: High-level overview of the end-to-end compilation workflow, including partitioning, synthesis, DPF, and hardware-aware mapping.

The decision matrix operates by comparing the $T$6-gate overhead of phase kickback against optimal standard synthesis across a sweep of register sizes, numbers of dyadic rotations, and desired precision. This ensures the DPF workflow never underperforms relative to the baseline.

Figure 2: Decision matrix comparing $T$7-gate counts between Phase Kickback and gridsynth for varying register sizes, dyadic $T$8 gate counts, and error thresholds.

Algorithmic Details and Ancilla Management

Phase kickback for dyadic rotations, implemented via a $T$9-qubit phase gradient register and efficient adders, achieves a per-gate $T$0-cost that, when amortized over several dyadic rotations, can be substantially less than that of repeated gridsynth decompositions. Ancilla overhead is controlled by the chosen maximum register size and is further mitigated by employing a shared phase gradient register for all DPF-extracted operations, serializing their execution to prevent a linear blow-up in qubit requirements with circuit width.

Due to the greedy, non-exhaustive nature of the DPF procedure, it is possible that not all configurations with minimal T-count are found; however, extensive empirical results suggest substantial real-world improvements.

Experimental Results

Benchmarking on a diverse suite of circuits—including QFT, QAE, QAOA, Hamiltonian simulation, quantum chemistry, physics simulation, and ML—demonstrates that the workflow achieves up to 70% $T$1-count reduction compared to state-of-the-art Clifford+$T$2 synthesis (gridsynth) and up to 60% over Repeat-Until-Success (RUS) circuits, while also reducing space-time volume by up to 60% for a range of surface code mapping strategies.

Figure 3: Normalized $T$3-gate counts for Baseline (gridsynth), Naive Phase Kickback, and DPF Synth across all benchmarks at stringent error thresholds.

Detailed analysis reveals:

• Naive application of phase kickback is often counterproductive, sometimes resulting in 10–80% higher $T$4-counts compared to optimal synthesis, underscoring the necessity of selective dyadic angle extraction.
• DPF consistently achieves non-inferior or superior T-count relative to the best of gridsynth or phase kickback across all circuits.
• The largest gains are observed in algorithm families with high densities of $T$5 gates and structured dyadic rotation usage (e.g., QFT, QAE).

  Figure 4: $T$6-gate counts for QFT under Phase Kickback versus gridsynth, illustrating rapidly diverging cost at reduced error threshold as dyadic structure is exploited.

The greedy dyadic extraction procedure dramatically concentrates the distribution of dyadic-structured rotations across the circuit post-synthesis, even when the input distribution is broad.

Figure 5: Distribution of dyadic $T$7 angles before and after Phase Kickback Synthesis.

Hardware Mapping and Space-Time Volume

Critically, the paper extends evaluation beyond logical gate counts by mapping the output circuits to logical surface code layouts using both Lightweight and Heavyweight Pauli Basis Computation strategies. The physical resource metric is space-time volume, computed as logical cycles times the total logical patch count. The outcomes demonstrate:

• T-count reduction often (but not always) translates into proportional space-time volume savings.
• For highly parallelizable circuits (e.g., QAE under LPBC), the serialization of phase kickback adders can increase depth and thus space-time volume, even as T-count falls.
• The mapping strategy mediates resource savings—HPBC can better absorb adder overhead into high-weight parallel operations, whereas LPBC suffers more from sequential CNOTs.
• The number of parallel phase gradient registers is a key additional parameter, trading off qubit count for schedule depth.

  Figure 6: Impact of the number of phase gradient states on logical circuit depth and space-time volume for QAE; optimal performance is achieved at an intermediate register count.

Comparison with Alternative Synthesis Techniques

By reparameterizing the decision matrix in terms of expected T-count for RUS rotation synthesis, the DPF workflow demonstrates generalizability; $T$8-count reductions persist, although the cross-over point for phase kickback relative to RUS is shifted, requiring more extracted dyadic rotations and higher precision than when using gridsynth.

Figure 7: Decision matrix comparing Phase Kickback versus RUS as a function of gate count and error threshold.

Figure 8: $T$9-gate counts under DPF Synth versus RUS-based rotation synthesis across benchmarks.

The framework thus applies to a spectrum of synthesis backends, remaining hardware-aware and optimizing according to the actual cost model.

Theoretical and Practical Implications

This work underscores three critical points for the fault-tolerant quantum compilation landscape:

• $R_z$0-count is not a universally reliable proxy for program cost; space-time volume under specific mapping and scheduling strategies more accurately reflects true hardware burden.
• Automatic detection and exploitation of dyadic structure, even when not apparent in the original algorithm, is key for resource minimization in large-scale quantum algorithms.
• Compiler design must account for physical architecture constraints, including ancilla register usage, adders' CNOT footprint, and available schedule parallelism, rather than assuming that logical-level gate minimization is sufficient.

The methodology also lays groundwork for future extensions, e.g., directly optimizing space-time volume via analytic modeling within the decision matrix, systematic allocation of multiple phase gradient registers, and enhanced co-optimization of routing, resource state preparation, and synthesis within a single toolchain.

Conclusion

Dyadic Phase Fixing pushes phase kickback from a specialized synthesis optimization into a general-purpose, numerically robust compilation primitive, capable of exploiting even latent dyadic rotation opportunities within arbitrary multi-qubit circuits. By embedding hardware-awareness and a flexible decision framework, it ensures no loss in T-count while strongly improving resource efficiency for broad algorithm classes and real hardware constraints.

This approach establishes new methodology for compilation workflows, motivating compiler research to move beyond gate count metrics to comprehensive program cost minimization and further architectural integration. The landscape for fault-tolerant code generation is thus advanced toward physically realistic and truly minimal executions.