Full Extractors for Logical Processing in Hypergraph Product Codes

Abstract: Quantum low-density parity-check (QLDPC) codes are promising candidates for practical low-overhead quantum memories. For large-scale fault-tolerant quantum computation, we further need logical processing methods for QLDPC codes. In this work, we construct full extractors -- surgery systems capable of measuring arbitrary logical Pauli operators on a code block -- for several hypergraph product (HGP) codes. These extractors enable logical processing via Pauli-based computation (PBC) without the compilation overhead observed in prior works. Moreover, our extractors have sizes between 50% and 80% of the base HGP codes, and the extractor-augmented codes can be supported on fixed connectivity hardware with maximum qubit degree ten. Our approach involves assembling many partial extractors with verifiable fault-tolerance into a single full extractor. For a distance 10 HGP code, circuit-level noise simulations yield logical measurement error rates of approximately $10<sup>{-6}$ at a physical error rate of 0.1%. These results demonstrate that extractor architectures, when designed in the fixed-connectivity setting, can achieve the space efficiency of QLDPC codes without introducing compilation overhead compared to surface code PBC architectures.

• The paper introduces a full extractor architecture that integrates multiple fault-tolerant partial extractors for arbitrary logical Pauli measurements in HGP QLDPC codes.
• It employs a modular design with fixed low-degree connectivity to achieve high measurement flexibility and resource efficiency.
• Circuit-level noise simulations demonstrate that the extractor-augmented system attains logical error rates around 10⁻⁶ under realistic depolarizing noise.

Full Extractors for Logical Processing in Hypergraph Product Codes

Introduction

This work systematically develops the design and analysis of full extractors—ancillary systems enabling arbitrary logical Pauli measurement via Pauli-based computation (PBC)—for hypergraph product (HGP) quantum low-density parity-check (QLDPC) codes. Specifically, the authors address the pivotal challenge of integrating logical processing capabilities into practical, low-overhead QLDPC-based architectures. By assembling multiple verifiably fault-tolerant partial extractors into a cohesive, fully-functional extractor, the construction achieves high measurement flexibility without the compilation overhead endemic to previous QLDPC and bicycle code "partial extractor" systems. The architectures are tailored to fixed low-degree connectivity (maximum degree ten), compatible with hardware such as superconducting qubits, and maintain favorable asymptotic and finite-size resource efficiency.

Hypergraph Product Codes and Logical Operator Structure

The foundation of the extractor system is the HGP code family, which is constructed from the parity-check matrices of two classical codes (taken in the cyclic case as $H_1 = H_2 = H$), yielding a CSS quantum code. Logical operators in HGP codes are highly structured: information sets for the classical codes map to explicit locations ("information qubits") on the physical HGP lattice, allowing canonical logical $X$ and $Z$ operators to be associated with specific columns and rows Figure 1.

Figure 1: An HGP code with highlighted logical $X$ and $Z$ operators; the extractor system supports local measurement gadgets on these canonical operators.

This algebraic structure is pivotal, as it enables modular extractor construction and distance analysis via reduction to properties of the seed classical codes and their information sets. Recent advances in cyclic HGP codes have demonstrated that block sizes and encoding rates can be optimized for practical quantum architectures.

Extractor System Design: Partial to Full Extractors

The extractor is a surgery system that interacts with the base code through a port assignment connecting base code physical qubits (support of logical operators) to graph vertices in the extractor ancilla system. Logical operator measurement is implemented by constructing a merged code which coherently augments the base code with ancillas, vertex checks, cycle checks, and appropriately deformed stabilizers.

The construction proceeds in three stages:

1. Single-column (partial) extractors: A distance-preserving partial extractor Figure 2 associated with a single column is constructed by reducing the distance determination problem to a subcode containing only the relevant base code qubits and extractor qubits. Using standard SAT solvers, the authors efficiently certify the fault tolerance of these gadgets for realistic code sizes.
2. Single-basis extractors: Multiple partial extractors (one per information column/row, coupled via bridging ancillas) are assembled into an extractor capable of measuring any basis-type logical (e.g., any $Z$ or any $X$ operator). The assembly leverages the symmetry and cyclicity of HGP codes to minimize ancilla overhead and maintain explicit connectivity guarantees. All logical operators in this subset are measured without requiring classical compilation/decomposition.

Figure 2: A $Z$ extractor formed by bridging single-column extractors; all logical $Z$ operators in the base code are accessible through this configuration.

1. Full extractors: The $X$ and $X$0 extractor systems are joined via a carefully designed bridge structure, resulting in a full extractor capable of implementing arbitrary logical Pauli measurements. The construction maintains controlled qubit degree and bounded bridge complexity.

Figure 4: Three different subsets of the full extractor, here using $X$1, with colored edges illustrating information flow between partial extractors and bridges.

Fault tolerance extends globally due to the local verifiability of each partial extractor and the explicit grafting structure.

Connectivity, Overhead, and Scalability

A salient feature of the proposed extractors is the ability to encode $X$2 logical qubits using block sizes close to that of the base HGP code—the extractor sizes range from 50% to 80% of the main code block. The architectures require only fixed local connectivity, with a maximum qubit degree of ten, as confirmed in explicit degree counts for practical examples.

Figure 5 details the connection pattern between extractors and the base code, including the vital port-to-vertex mapping for information qubits and the necessary additional bridge connectivity for logical operator commutativity and parallelizable measurement.

Figure 6: Connectivity maps between $X$3/$X$4 extractors and the base code, and the added bridge network for the full extractor system enabling all logical measurements.

These results compare favorably to previous architectures using reconfigurable connectivity or incurring substantial compilation overhead for arbitrary logical operator processing.

Fault Tolerance and Error Suppression

The authors conduct full circuit-level noise simulations for a distance-10 HGP code instance with a 50-logical qubit block ($X$5). They demonstrate that their extractor-augmented code, under a circuit-level depolarizing noise model with $X$6, achieves logical measurement error rates on arbitrary (including high-weight and non-CSS) logicals of approximately $X$7, comparable to state-of-the-art thresholds for surface code PBC systems. Importantly, the extractor does not measurably degrade the preservation of other logical qubits during non-demolition measurement of a selected observable.

Figure 7: Logical error rates for HGP+extractor system over a range of physical error rates and syndrome measurement rounds, compared with the base HGP code (memory experiment).

Decoder design utilizes a two-stage approach (Relay-BP followed by ILP fallback), and further analysis highlights the challenges and opportunities in practical decoder engineering for these large block codes and complex circuits.

Figure 9: Comparison of logical measurement error rates under the two-stage decoder and baseline methods, with error bars corresponding to high-confidence intervals.

Theoretical Implications and Open Questions

This work substantiates that fully universal, distance-preserving logical measurement can be implemented in QLDPC codes with low space and connectivity overhead, closing a crucial gap between theoretical code properties and physical architectures. The modular, verifiable construction of extractors establishes a blueprint for extension to more general QLDPC code families (lifted product, balanced product, ultra-high-rate QLDPCs) and sets the stage for library-style compilation of logical measurement protocols in arbitrary hardware settings.

The explicit reduction of distance verification to small subcodes provides a practical and scalable path for code/protocol certification even as block sizes increase.

Several avenues for future work are identified:

• Algorithmic decoders: Replacing ILP-based decoding with high-speed approximate algorithms potentially based on reinforcement learning or further tuned belief propagation.
• Syndrome measurement circuits: Engineering short-depth, low-hook-error measurement schedules exploiting the extractor structure.
• Advanced QLDPC families: Porting the assembly techniques to ultra-high-rate codes or those with favorable locality for modular hardware.
• Parallelism and circuit resources: Integrating extractor-based parallel measurement, magic state distillation, and optimized resource estimation in the megaquop (million-logical operation) regime.

Conclusion

Extractor architectures as constructed in this study provide a rigorous, efficient, and hardware-friendly route to supporting universal logical measurement (and thereby universal fault-tolerant quantum computing) within practical QLDPC codes. The modular methodology—grounded in both combinatorial coding and graph-theoretical properties—presents a scalable paradigm for future quantum information processing platforms seeking to overcome the bottlenecks inherent in surface codes and compilation-heavy QLDPC approaches.

The techniques and results herein will inform both the design of next-generation QLDPC-based quantum hardware and the theoretical development of resource-efficient, abstraction-friendly compiler toolchains for quantum algorithms.