LP5X-PIM Sim: A High-Fidelity HW/SW Integrated Simulator for LPDDR5X-PIM

Abstract: This tech note describes the architecture and execution results of the LPDDR5X-PIM simulator, developed by Samsung Electronics. Based on the latest research and internal specifications, the simulator provides a high-fidelity model of both the hardware data paths and the software control layers of the LPDDR5X-PIM block. This integrated hardware-software simulation approach enables precise evaluation of system performance and energy efficiency while maximizing PIM resource utilization. We have refined existing simulation frameworks to align with actual hardware implementation, ensuring consistent behavioral accuracy. Further technical details regarding the specific architecture and circuit design of the LPDDR5X-PIM will be disclosed in future publications

• The paper introduces a cycle-accurate simulator that integrates LPDDR5X-PIM hardware models with a comprehensive PIM-aware software stack.
• It models both memory controller operations and PIM devices to achieve up to 6.2× speedup on matrix-vector (GEMV) workloads.
• Reshape optimization in the software stack provides an additional 1.65× speedup, enabling effective design-space exploration and benchmark validation.

LP5X-PIM Sim: A High-Fidelity Simulator for LPDDR5X-PIM Hardware-Software Integration

Motivation and Background

Processing-in-memory (PIM) architectures aim to address the fundamental bottlenecks of memory-bound computation by integrating compute-capable logic within DRAM modules, thereby reducing data movement and improving throughput and energy efficiency. While numerous simulators exist for generic HBM or DDR-based PIM, none provide comprehensive modeling for commercial LPDDR5X-PIM (LP5X-PIM) architectures at both the hardware and software stack levels. This deficit is especially significant as LPDDR5X becomes prevalent in mobile and edge computing for AI workloads. The work introduces LP5X-PIM Sim, a cycle-accurate, high-fidelity simulator that models both the specific datapath architecture of Samsung’s LP5X-PIM and the PIM-aware software stack, tightly integrating hardware and software behaviors at a granular level.

Figure 1: LP5X-PIM Sim block diagram highlighting the hardware-software integration and controller interactions.

Simulator Architecture and Modeling

Hardware Model: Memory Controller and LP5X-PIM Device

The simulator decomposes the hardware aspect into two principal modules: the memory controller and the LP5X-PIM device. The memory controller parses and schedules memory requests, ensuring adherence to JEDEC LPDDR5X timing constraints at the cycle level. The LP5X-PIM device encompasses DRAM banks with dedicated in-memory compute blocks and PIM registers in a one-to-one bank-to-block mapping. This architectural choice enables parallel compute-augmented memory requests, maximizing bank-level parallelism and eliminating the off-chip bandwidth bottleneck.

Software Model: PIM Kernel Layer

The PIM Kernel, implemented in software, is responsible for mediating application execution and managing hardware resources. It consists of the DataMapper (offline, static data placement) and the PIM Executor (runtime orchestration):

• DataMapper: Transforms input tensors or matrices into “PIM tiles” according to hardware constraints, organizing the memory layout to optimize locality and avoid runtime overhead.
• PIM Executor: Dynamically performs code generation, manages mode transitions (Single-Bank for standard DRAM, Multi-Bank for PIM bulk processing), and drives GEMV execution per tile using the PIM-specific ISA.

  Figure 2: Execution flow of the PIM kernel, separating DataMapper (offline) and PIM Executor (runtime) roles.

Address Mapping and Tiling Strategies

Efficient mapping and data tiling are critical for harnessing the aggregate compute bandwidth of the LP5X-PIM. The simulator supports sophisticated schemes:

• Vertical Mapping: Distributes tile rows sequentially across (Channel, Rank, Bank Group, Bank), maximizing concurrency.
• Horizontal Mapping: Co-locates adjacent columns in a tile within a bank to optimize row buffer hit rates.
• Reshape Optimization: For small or skewed matrices, applies column-based tiling to avoid underutilization of PIM blocks, ensuring near-peak hardware utilization.

  Figure 3: Demonstration of the matrix-to-tile partitioning and physical allocation across DRAM banks.

Performance Evaluation

GEMV Acceleration Baseline

The simulation campaign targets matrix-vector multiplication (GEMV) as a canonical memory-bound operation, evaluating speedup over a sequential non-PIM baseline across a grid of tile sizes, data types (INT/FLOAT, various bitwidths), and vector/matrix dimensions. In a scenario without memory-fence overhead (idealized reordering guarantee), LP5X-PIM achieves up to 6.2$\times$ speedup for large 4096-dimension workloads when employing favorable tile shapes (e.g., W8A8, W4A4, W8A8 FP). Configurations with smaller tiles see a speedup reduction due to increased register loading overhead.

Figure 4: Speedup ratios of LP5X-PIM Sim versus non-PIM baseline GEMV, excluding memory-fence penalties.

Impact of Memory-Fence Latency

In practical multiprocessor systems, memory-fence instructions (e.g., 150ns penalty per fence) are mandated to enforce sequential tile execution, amortized by large computational loads but more acute when tile granularity is small. With fences, the worst-case speedup decreases (e.g., to 4.1$\times$ for small tiles at W4A16) yet remains above 5.0$\times$ for most tile/data configurations and dimensions above 2048.

Software Stack Optimization: Reshape

By activating the Reshape optimization—which partitions small matrices both row- and column-wise—PIM block utilization approaches full occupancy even for unfavorable input dimensions. Simulation quantifies the gain: up to 1.65$\times$ additional speedup compared to traditional row-only partitioning. This validates the necessity of co-designing the software stack to realize hardware potential, especially for irregular AI workloads.

Implications and Future Directions

The LP5X-PIM Sim provides a robust platform for exploring architectural and software-level co-optimizations under true cycle-level behavioral realism. The high-fidelity modeling of Samsung’s proprietary hardware, coupled with the ability to explore PIM-aware kernel optimizations, offers value in:

• Design-Space Exploration: Fine-grained tiling/placement strategies and their performance/energy impact can be exhaustively evaluated before silicon implementation.
• System Software Development: Runtime and offline partitioners can be benchmarked to maximize bank-level and register-level efficiency under diverse application constraints.
• Accurate Benchmarking: Empirical evaluation of PIM under real LPDDR5X timing and bandwidth constraints sets the stage for trustworthy comparison with HBM- or DDR-based systems.

In terms of broader AI impact, PIM simulation at this detail level is essential for scaling next-generation LLM inference and training in resource-constrained edge/mobile platforms, where memory bandwidth is the key limiter.

Conclusion

LP5X-PIM Sim establishes a new standard for hardware-software co-simulation in commercial LPDDR5X-PIM systems, underpinned by thorough integration of cycle-accurate hardware models and PIM kernel stacks. The simulator demonstrates substantial speedup for practical GEMV workloads—as high as 6.2$\times$ baseline, with further 1.65$\times$ augmentation via software tiling optimizations. This work creates a foundational tool for future PIM architecture research, design optimization, and software stack validation, with implications extending to both theoretical exploration and practical deployment in edge AI systems (2606.00636).