Workload-Aware Early-Stage Power Delivery Network Optimization via Architectural Power Traces

Abstract: Power Delivery Networks (PDNs) are critical for maintaining voltage integrity in modern multiprocessor systems. Conventional early-stage PDN planning relies on static or worst-case power assumptions, often leading to over-provisioned designs and inefficient use of routing resources. This paper proposes a workload-aware methodology for early-stage PDN optimization based on architectural power traces. Using architectural simulations, temporal power activity is captured at fine granularity and mapped to spatial power density distributions across the chip. These distributions are then translated into current demand profiles to guide PDN topology planning at tile granularity. By incorporating realistic workload behavior, the proposed approach enables adaptive PDN resource allocation during early design stages. Experimental results demonstrate that the method achieves up to 32.94% reduction in PDN metal area compared to conventional worst-case designs, while maintaining compliance with IR drop and electromigration constraints.

• The paper introduces a workload-aware PDN planning method that maps architectural power traces to tile-level demand and adaptively allocates grid wires by power class.
• The method reduces PDN metal area by approximately 30–33% across 4-core and 16-core systems, PARSEC and SPLASH-2 workloads, temperatures, and average- or peak-power provisioning.
• The optimized grids meet IR-drop and electromigration constraints, but threshold selection, parasitic modeling, heterogeneous architectures, and multi-workload provisioning remain open challenges.

This paper presents a workload-aware methodology for early-stage Power Delivery Network (PDN) planning that replaces conventional worst-case power assumptions with spatial power demand profiles derived from architectural simulation. The central claim is that early-stage PDN sizing, when guided by tile-level current demand extracted from microarchitectural power traces, can reduce PDN metal area by up to 32.94% relative to uniformly provisioned worst-case grids while remaining compliant with IR drop and electromigration (EM) constraints.

Motivation and background

Conventional early-stage PDN planning sizes a regular multi-layer grid of orthogonal power stripes using conservative global power assumptions. For each region $i$, current demand is approximated as $I_i = P_i / V_{dd}$, and the grid is dimensioned so that voltage drop satisfies $\Delta V_i \leq \Delta V_{\max}$ and wire current densities remain below EM limits. Because actual power consumption in multiprocessor systems is strongly non-uniform and workload-dependent, this guardbanded approach over-provisions metal resources, particularly in low-activity regions. The authors illustrate this with a motivational comparison between a uniform dense grid and an adaptively allocated grid whose density tracks spatial power demand.

The work builds on prior lines of research: sensitivity-based topology optimization of structured power/ground networks [pdnopt], analytical early-stage grid analysis under uncertain working modes [1424171], system-level automatic PDN generation for multiprocessors from architectural and floorplan information [maria], and machine-learning-based prediction of grid behavior to reduce iterative simulation cost [9516776]. The distinguishing contribution of this paper is the use of workload-derived architectural power traces as the driver for adaptive PDN resource allocation at tile granularity during early design stages.

Proposed methodology

The methodology proceeds in four stages.

Architectural power trace extraction. Temporal power traces are collected with HotSniper [8444047], a Sniper-based many-core simulation toolchain providing cycle-level performance modeling coupled with per-component power estimation. Power is monitored at sub-core granularity across components such as integer ALUs, FPUs, reorder buffers, branch predictors, and instruction caches, capturing dynamic variation due to instruction mix, memory behavior, and execution intensity. Two provisioning modes are evaluated: temporally averaged traces (workload-specific average behavior) and per-tile maximum observed power (conservative peak-aware provisioning).

Spatial power density mapping. Each architectural component $k$ is mapped to its physical floorplan region, and component powers are aggregated onto tiles: $P_i = \sum_{k \in \mathcal{K}_i} \bar{P}_k$, yielding tile-level power density $\rho_i = P_i / A_i$ and current demand $I_i = P_i / V_{dd}$.

Subcore power classification. Tiles are classified by normalized power $p_i = P_i / P_{\max}$ into high ($T_H \leq p_i \leq 1$), medium ($T_M \leq p_i < T_H$), and low ($I_i = P_i / V_{dd}$0) classes, where $I_i = P_i / V_{dd}$1 and $I_i = P_i / V_{dd}$2 are user-tunable thresholds that trade off hotspot mitigation against routing overhead.

Adaptive grid construction. A uniform skeleton grid of candidate wire locations is defined, sized so its densest configuration supports $I_i = P_i / V_{dd}$3. Wires are then instantiated in three passes: all skeleton lines through high-power tiles, every $I_i = P_i / V_{dd}$4-th line through medium-power tiles, and every $I_i = P_i / V_{dd}$5-th line through low-power tiles. Tile currents are distributed uniformly across intersecting grid nodes, $I_i = P_i / V_{dd}$6, preserving spatial power characteristics in a tractable resistive abstraction with ideal boundary voltage sources.

Experimental evaluation

Experiments use 4-core and 16-core configurations running PARSEC and SPLASH-2 multithreaded benchmarks at maximum parallelism, simulated at 1 GHz and 2 GHz, with traces collected under varying operating temperatures (0 °C, 40 °C, 65 °C). Classification thresholds were fixed at $I_i = P_i / V_{dd}$7 and $I_i = P_i / V_{dd}$8. All reductions are reported relative to a uniform worst-case-provisioned baseline:

Cores	Temp (°C)	Avg. power reduction	Peak power reduction
4	0	32.94%	29.05%
4	40	32.12%	29.05%
4	65	32.93%	29.05%
16	0	32.57%	30.31%
16	40	32.45%	30.31%
16	65	30.54%	30.31%

Three observations follow directly from these results. First, savings are consistently in the 30–33% range across both core counts, temperatures, and provisioning modes, indicating robustness of the approach to operating conditions. Second, average-power-based provisioning yields up to 3.9 percentage points more area savings than peak-power-based provisioning, quantifying the additional over-provisioning incurred even when only per-tile peaks are used rather than global worst-case assumptions. Third, and most importantly, all configurations satisfy IR drop and EM constraints without violations, so the metal-area reduction does not come at the cost of reliability compliance within the evaluated model.

Limitations and open questions

Several limitations are implicit or explicit in the work. The methodology relies on architectural layout assumptions mapping components to physical regions, and interconnect parasitics are approximated with resistive tile-level abstractions; inductive effects such as ground bounce, which the introduction identifies as a modern PDN concern, are not modeled in the early-stage analysis. The classification thresholds $I_i = P_i / V_{dd}$9 and $\Delta V_i \leq \Delta V_{\max}$0, the sampling parameter $\Delta V_i \leq \Delta V_{\max}$1, and the pad locations are user-defined rather than optimized, leaving open how sensitive the reported savings are to these choices. The evaluation covers homogeneous multicore configurations at moderate scale; applicability to heterogeneous architectures and finer technology nodes is untested. Finally, because separate PDN configurations are synthesized per workload scenario, the paper leaves open how a single design should be provisioned when multiple workloads with divergent spatial power profiles must share one silicon implementation — a question of practical consequence for production designs.

Conclusion

The paper demonstrates that architectural power traces can serve as an effective early-stage proxy for spatial current demand in PDN planning. By classifying tiles by normalized power and instantiating grid wires proportionally, the method achieves approximately 30–33% PDN metal area reduction versus worst-case uniform provisioning across PARSEC and SPLASH-2 workloads on 4-core and 16-core systems, without IR drop or EM violations. The results substantiate the claim that conventional worst-case PDN design substantially over-provisions routing resources, while identifying threshold tuning and multi-workload co-provisioning as open problems.