Practical Log-Depth Quantum State Preparation and Circuit Verification via Tree Tensor Network Compilation

Abstract: Matrix product states provide efficient classical descriptions of quantum systems that may be useful as reference states for quantum algorithms such as quantum phase estimation and quantum-selected configuration interaction. Shallow circuit constructions for loading matrix product states onto quantum computers is necessary for this to be practical on near-term hardware. We present a decomposition of matrix product states to log-depth quantum circuits via a simple tree tensor network renormalisation procedure. Our method exposes an explicit parameter which can be used to trade a small amount of fidelity for large savings in circuit depth. We extend this decomposition to the case of matrix product operators allowing us to construct log-depth and ancilla-free circuits to calculate overlaps of the form $\left |\langleφ|U|ψ\rangle\right |<sup>2$. In particular, we demonstrate an interpretation of these circuits as \emph{verifier circuits} with application to circuit-level device calibration.

• The paper introduces a TTN-based pipeline that compiles MPS into log-depth circuits to overcome the linear depth bottleneck in direct quantum state preparation.
• The method uses merge-based SVDs and bond dimension truncation to trade off fidelity and circuit depth, achieving high fidelity for up to 20 qubits.
• The paper also presents an ancilla-free verifier circuit for MPOs, enabling efficient overlap estimation and device calibration on NISQ hardware.

Practical Log-Depth Quantum State Preparation and Circuit Verification via Tree Tensor Network Compilation

Introduction and Motivation

Efficient quantum state preparation remains a critical bottleneck for realizing practical quantum algorithms, particularly in quantum chemistry applications such as quantum phase estimation (QPE) and quantum-selected configuration interaction (QSCI). The efficacy of these algorithms relies heavily on the quality and practicality of initial state encodings. Matrix product states (MPS) offer computationally tractable classical representations for many physically relevant states and form reference states for quantum simulation. However, circuit depth constraints on noisy intermediate-scale quantum (NISQ) devices limit the feasibility of direct MPS-to-circuit constructions due to linear depth or high transpilation overhead induced by multi-qubit gates in standard approaches.

The work introduces an explicit, tunable pipeline for compiling MPS into logarithmic-depth quantum circuits using a tree tensor network (TTN) transformation via merge-based local singular value decompositions (SVDs). This approach enables a direct trade-off between state preparation fidelity and circuit depth by truncating bond dimensions during renormalization. The technique naturally generalizes to the preparation of matrix product operators (MPO), allowing for ancilla-free, log-depth verifier circuits that compute overlaps of the form $|\langle\phi|U|\psi\rangle|^2$. The implications extend to efficient fidelity estimation and circuit-level device calibration for quantum processors.

Tensor Network Formalism and Circuit Mappings

The tensor network graphical calculus treats quantum states as interconnected tensors, with legs denoting physical and virtual indices. MPS and MPOs structure these tensors sequentially, with the maximum internal dimension—the bond dimension $\chi$—controlling both expressivity and resource requirements.

Figure 1: Basic tensors as depicted in tensor network notation, which serve as the formal building blocks for complex quantum states.

Typical MPS-to-circuit mappings implement a staircase arrangement, with each step corresponding to a multi-qubit isometry embedded in a unitary operator. These constructions entail a depth scaling as $\mathcal{O}(N)$ for $N$-qubit systems and gate sizes of up to $1+\log\chi$ qubits. While such mappings can be slightly optimized by midpoint initialization or ansatz-based layering, the fundamental linear asymptotic scaling persists.

Figure 2: Example structures for both a 4-site MPS and MPO, where external legs map to qubit subsystems and internal virtual bonds reflect entanglement capacity.

This linear depth barrier can be overcome by leveraging TTNs, which admit log-depth mappings but lack well-established ground-state optimization algorithms on par with density-matrix renormalization group (DMRG) procedures for MPSs.

Figure 3: A canonical MPS is mapped to a linear-depth staircase circuit, illustrating the bottleneck in standard approaches.

Figure 4: Mapping a 3-layer TTN with orthogonality centered at the root enables a direct log-depth circuit compilation.

Renormalization and Log-Depth Compilation

The Renormalization Procedure

The central algorithm recursively merges pairs of neighboring MPS sites and applies SVDs to yield a TTN configuration. At each step, bond dimensions may be truncated to a fixed power of two, balancing fidelity loss and gate size reduction. This process produces a $\lceil \log_2 N \rceil$-layer tree structure, culminating in a hierarchy where all gates (isometries embedded in unitary operators) are mapped sequentially onto the quantum hardware.

Figure 5: Successive local merges and SVDs renormalize an MPS into the binary TTN suitable for efficient compilation.

Complexity and Circuit Resource Analysis

Without truncation, the maximal bond dimension can increase to $\chi^2$, resulting in possible $4\log\chi$-qubit gates for sufficiently large $N$. Numerical analysis validates that above a threshold number of qubits, the gate size saturates and is independent of $N$, implying that circuit depth asymptotically remains logarithmic in system size.

Figure 6: Maximal gate size as a function of MPS bond dimension and number of sites, confirming the independence from $\chi$0 beyond a regime.

Exact TTN-based circuits demonstrate log-depth scaling even after transpilation to hardware-constrained topologies (all-to-all, square grid, heavy-hex connectivity). However, the transpilation overhead from large multi-qubit gates leads to impractically high circuit depths for large bond dimensions.

Figure 7: Post-transpilation circuit depth as a function of qubit number for exact preparation, highlighting overhead on real architectures and the impact of MPS bond dimension.

Approximate Decomposition: Fidelity-Depth Trade-Off

Circuit complexity is markedly improved by enforcing a strict gate size cut-off—e.g., truncating to bond dimension two such that only $\chi$1-qubit gates are realized. The resultant circuits exhibit a practical fidelity-depth trade-off. Empirical findings indicate that the infidelity grows linearly with system size but with small prefactors, maintaining high fidelity for up to at least 20 qubits (fidelity $\chi$2) and only moderate decay for much larger systems.

Figure 8: Top: Circuit depth for approximate preparation (bond dimension $\chi$3, $\chi$4, $\chi$5) on different hardware models; Bottom: Extrapolated log-performance for larger system sizes indicating suitability for near-term hardware.

These truncated circuits achieve logarithmic depth and practical runtimes, making MPS-based quantum algorithm warm-starts feasible even for hundreds of qubits on NISQ-class architecture.

Log-Depth Verifier Circuit Construction for MPOs

Vectorization and Overlap Circuits

The extension to operators proceeds by vectorizing the MPO through interpreting both input and output legs as physical qubit indices, then recasting this doubled system as an MPS followed by log-depth compilation.

Figure 9: MPO vectorization and SVD sequence produces a corresponding MPS, enabling reuse of the state preparation framework.

The resulting circuit $\chi$6 on $\chi$7 qubits computes overlaps $\chi$8, directly returning this quantity as a computational basis amplitude. This generalizes standard approaches (e.g., SWAP test, requiring ancillas) and is applicable when $\chi$9 admits a low-bond-dimension MPO description.

Validation and Performance Metrics

Direct comparisons between classically computed overlaps and the verifier circuit outputs confirm correctness and exactness in the absence of shot noise.

Figure 10: Parity between direct overlap calculation and log-depth verifier circuit output validates the construction for unitary MPOs.

Shot-based estimation introduces $\mathcal{O}(N)$0 statistical noise, as expected.

Figure 11: Error decay with increasing shot counts for the verifier circuit, reflecting standard quantum measurement statistics.

The verifier circuit is sensitive to implementation noise, providing a monotonic fidelity metric that can be leveraged for device calibration and benchmarking.

Figure 12: Verifier circuit output provides a monotonically decreasing fidelity signal as applied noise increases, supporting its utility for circuit-level calibration.

Theoretical and Practical Implications

Formally, this work provides a constructive method for log-depth state and operator preparation with analytically tunable fidelity versus resource constraints, thereby bypassing the intractable overheads endemic to linear-depth MPS compilations. It extends the landscape of efficient quantum state initialization by delivering hardware-agnostic, practical circuits for important quantum chemistry applications, enabling warm-start DMRG-based QPE or QSCI workflows.

The verifier circuit formulation has substantial implications for quantum processor characterization, providing a scalable ancilla-free alternative to the SWAP test and a tool for benchmarking and error mitigation. The strategy bridges classical tensor network solvers and quantum state/operation injection with rigorous control over depth and infidelity, laying ground for more robust hybrid-quantum-classical pipelines.

The analytic nature of the mapping sets it apart from variational quantum compiling or measurement-and-feed-forward based schemes, which are not currently practical for large-scale or NISQ systems.

Conclusion

This work delivers a practical and scalable algorithmic framework for quantum state and operator preparation with explicit, controllable log-depth quantum circuits. The methodology scales to large qubit systems without incurring explosive gate count overhead and enables direct integration of tensor network-grown (e.g., DMRG) initializations for near-term quantum algorithms. The verifier circuit construction further expands the utility of the approach to device calibration and error quantification, with empirical fidelity scaling supporting large-scale deployments.

Future work could extend these constructions to projected entangled pair states (PEPS), integrate with classical state tailoring for chemistry and materials simulation, and explore the effect of noise and gate error in real device settings through systematic calibration campaigns.

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Reference: "Practical Log-Depth Quantum State Preparation and Circuit Verification via Tree Tensor Network Compilation" (2605.06579)