PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation

Abstract: Modern hardware compilers increasingly rely on rich intermediate representations (IRs) to preserve optimization-relevant semantics before generating RTL code. However, one important optimization is still largely deferred to backend tools: pipeline optimization. In common RTL flows, registers are inserted by frontend heuristics or hardware designers and later adjusted by backend retiming after the design has been lowered to a much lower-level netlist representation. At that point, much of the operator-level structure originally exposed by the compiler IR has already been weakened or lost, limiting opportunities for global, compiler-level pipeline optimization. This paper presents PipeRTL, an IR-level pipeline optimization framework for hardware compilers, instantiated in CIRCT. PipeRTL makes the legality of register relocation explicit in the IR, uses a learned timing predictor to approximate downstream delay behavior, and formulates timing-aware register relocation as a global min-cost flow problem under timing constraints. Evaluation on open-source designs under a commercial backend synthesis flow shows that PipeRTL improves downstream implementation quality on average, reducing critical-path delay, power, and area across the evaluated benchmarks, while also providing a stronger starting point for backend retiming. These results indicate that exposing pipeline optimization as an explicit compiler pass can deliver backend-meaningful gains by improving the sequential structure presented to later stages and the resulting downstream implementation quality.

• The paper introduces IR-level pipeline optimization using a custom {Pipe} dialect combined with an XGBoost-based timing predictor for informed register relocation.
• It formulates the optimization as a min-cost flow problem, achieving significant improvements in register count, critical path delay, power, and area.
• Empirical evaluations on diverse hardware designs reveal nearly 19.8% register reduction and notable PPA gains with negligible runtime overhead.

PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation

Motivation and Problem Statement

Register placement within hardware designs critically impacts performance, power, and area, yet pipeline optimization is typically relegated to backend tools operating on lowered netlists, where semantic information from high-level IRs is largely lost. Common frontend flows, including HLS and agile hardware frameworks, lack downstream-aware optimization loops for pipeline placement; their heuristics are later revised via backend retiming algorithms with only partial visibility into the initial structural semantics. This separation restricts the scope and efficacy of pipeline optimization, limiting global analysis and the ability to preserve functionally and structurally legal transformations at the IR level.

PipeRTL addresses this gap by formulating pipeline optimization as a compiler middle-end problem, leveraging the semantic richness of hardware IRs prior to backend lowering. It explicitly models sequential legality, stage potentials, delay boundaries, and source/sink constraints within a custom MLIR {Pipe} dialect. The approach enables the optimization of register relocation using global objectives, directly informed by learned timing cost models approximating downstream delay behavior.

PipeRTL Framework Architecture

PipeRTL is integrated into CIRCT, reusing its frontend infrastructure to operate uniformly across HDLs. The framework implements a transformation flow that (1) translates input designs into CIRCT core dialects, (2) rewrites them into the {Pipe} dialect, (3) annotates combinational nodes with timing predictions via XGBoost-based regressors, and (4) formulates timing-aware register relocation as a min-cost flow optimization under explicit legality and timing constraints. The optimized design is then lowered back to standard CIRCT dialects for downstream synthesis or simulation.

Figure 1: Overall framework of PipeRTL, illustrating the transformation passes and optimization pipeline.

IR-Level Representation and Legal Transformations

The {Pipe} dialect encodes hardware designs as weighted directed graphs ("wGraph"), wherein nodes represent combinational operations and boundary nodes, and edges encode register counts and data capacity. PipeRTL introduces specialized primitives (pipe.delay, pipe.bubble, pipe.pin, pipe.sink) to make sequential boundaries, broadcast structures, and IO constraints explicit. Stage updates ($\Delta s(v)$) are recorded via pipe.potential, allowing systematic combinational propagation that maintains legal cycle counts along all pin-to-sink paths.

Figure 2: IR transformation flow of PipeRTL with pipeline legality for stage potentials and delays.

Figure 3: Example IIR design and corresponding wGraph representation exposing explicit sequential structure.

Timing Prediction and Global Optimization Formulation

Accurate timing modeling is critical since IRs lack physical operator delays. PipeRTL adopts an XGBoost-based learned timing predictor, trained on features extracted from the CIRCT Comb dialect (operation type, operand count, bitwidth), yielding robust regression metrics (RMSE: 42.041, $R^2$: 0.997 for single operations; $R^2$: 0.881 for paths). This predictor guides the estimation of critical path delays for timing-aware optimization.

Figure 4: Training and inference flow of the XGBoost-based timing predictor used for operation delay annotation.

The core optimization is formulated as a min-cost flow problem:

$$\min \sum_{v \in V} \Delta s(v) \cdot \Bigg(\sum_{s \prec v}\beta(e_{s, v}) - \sum_{s \succ v}\beta(e_{v, s})\Bigg)$$

subject to legality ($w'(e_{u, v}) \geq 0$) and timing constraints for all critical pin-sink paths ($$W(u \rightsquigarrow v) + \Delta s(v) - \Delta s(u) > 0$$). Target delay searching via binary search tightens feasibility and ensures optimal solutions are consistent with backend implementation constraints.

Evaluation and Empirical Analysis

PipeRTL was evaluated using open-source processor and accelerator modules (BOOM, Gemmini, Xiangshan, TensorLib, WinoGen) across diverse categories (memory, systolic arrays, FIFO, IP generators), synthesized with Design Compiler and ASAP7 PDK. Structural optimization via PipeRTL yields an average register reduction of 19.8% and register data capacity reduction of 12.6% across benchmarks.

Figure 5: Register and register data capacity reduction achieved by PipeRTL across benchmark designs.

Downstream PPA improvements (critical path delay, dynamic power, cell leakage, total cell area) are consistently observed both with and without backend retiming. PipeRTL produces sequential structures with 2.3% shorter average critical paths and up to 6.6% reduction in power and 5.4% area reduction when retiming is enabled, demonstrating its complementary nature. Ablation removing timing constraints confirms that legality-preserving transformations alone are insufficient: timing-aware objectives are required to avoid degraded critical paths and detrimental downstream synthesis results.

PipeRTL's sequential structures are robust under extensive target clock sweeps, with stable power and area profiles exceeding those of the original designs, even through place-and-route (PnR) phases. The runtime overhead of PipeRTL is negligible compared to backend retiming, with average speedups of over two orders of magnitude.

Figure 6: PPA evaluation of the Gemmini design under target-clock sweep, exhibiting superior stability and efficiency with PipeRTL.

Practical and Theoretical Implications

PipeRTL advances compiler architecture for hardware design by introducing explicit IR-level legality and timing semantics for pipeline optimization. It achieves demonstrable backend-meaningful gains while remaining computationally tractable as a compiler pass. The ability to globally restructure pipelines at the IR stage—prior to lowering into less structured netlists—enables richer optimization spaces inaccessible to traditional backend retiming. The framework is extensible to further timing models, new dialects, or hybrid optimization objectives, supporting accelerated hardware design cycles in increasingly complex systems.

Speculation on Future Developments

IR-level pipeline optimization via frameworks such as PipeRTL suggests a convergence between software-style compiler techniques and hardware synthesis methodologies, potentially permitting more integration between scheduling, resource allocation, and physical design. Future extensions could incorporate richer physical constraints, extend predictor designs to incorporate layout-aware delay modeling, or integrate formal verification for legality of transformations. The adoption of such compiler passes in standard toolchains may shift pipeline decision-making from heuristic/manual approaches to data-driven and globally optimal strategies, enhancing hardware compilation productivity and backend efficiency.

Conclusion

PipeRTL demonstrates that explicit IR-level semantics and timing-aware global optimization yield measurable improvements in hardware RTL generation. By integrating legality, timing, and resource metrics within the compiler middle-end, the framework advances the scope of hardware compilers to include sequential optimization passes, producing optimized designs that complement backend synthesis and retiming. This approach is scalable, extensible, and computationally efficient, deepening the capacity for hardware compilers to reason about pipeline structures and optimization-relevant semantics prior to backend lowering (2605.01836).