Maximizing Memory-Level Parallelism via Integrated Stochastic Logic-in-Memory Architectures

Abstract: Today's high-performance architectures are increasingly constrained by data movement latency and energy overhead, as the slowdown of single-core performance scaling coincides with the rise of highly data-intensive workloads. In-memory architectures have emerged as a complementary solution to conventional von Neumann systems by alleviating memory bandwidth bottlenecks, exploiting massive concurrency, and mitigating excessive data movement between memory and processing units. This study proposes a parallel in-memory stochastic computing (SC) architecture that implements an end-to-end computation pipeline within Magnetic Tunnel Junction (MTJ)-based memory augmented with logic-in-memory (LIM) capabilities. By leveraging the inherent stochasticity and write-read characteristics of MTJ devices, the proposed architecture enables a fully parallel and deterministic conversion of binary operands into probabilistic bit-streams, eliminating the need for energy-intensive external random number generation circuitry. These bit-streams are processed by parallel stochastic arithmetic units integrated directly within the memory arrays to efficiently implement core arithmetic and transcendental functions with minimal hardware complexity and inherent noise tolerance. The resulting stochastic outputs can be either reused as an input of future stochastic processing or converted back to binary form using parallel accumulation mechanisms and stored in the MTJ memory. By tightly integrating data storage, bit-stream generation, and computation within a unified in-memory fabric, the proposed design maximizes memory-level parallelism while substantially minimizing data movement.

• The paper introduces an MTJ-based LIM structure that integrates deterministic bit-stream mapping for parallel stochastic computing.
• It achieves up to 22×–64× speedup over serial stochastic computing with latency improvements exceeding three orders of magnitude.
• Extensive simulation confirms enhanced fault tolerance, energy efficiency, and scalable performance for complex data-intensive workloads.

Maximizing Memory-Level Parallelism via Integrated Stochastic Logic-in-Memory Architectures

Introduction

"Maximizing Memory-Level Parallelism via Integrated Stochastic Logic-in-Memory Architectures" (2604.23146) introduces an MTJ-based in-memory architecture implementing parallel stochastic computing (SC) with Logic-in-Memory (LIM) devices, targeting performance bottlenecks in contemporary data-intensive workloads. The design exploits native memory-level parallelism, deterministic bit-stream generation, and direct in-array stochastic arithmetic for both basic and transcendental functions, achieving substantial latency reduction and energy efficiency compared to conventional serial SC and state-of-the-art in-memory computing (IMC) alternatives.

Stochastic Computing Fundamentals and Bit-Stream Generation

Stochastic computing replaces traditional binary arithmetic with probabilistic bit-streams, enabling arithmetic operations with minimal hardware. Fig. 1 delineates common approaches for generating bit-streams, including uncorrelated, correlated, serial, and massively parallel generation.

Figure 1: Conventional SC bit-stream generation approaches and their correlation and temporal properties.

Arithmetic operations are realized with simple logic gates; some require correlated inputs (e.g., minimum/maximum), others demand uncorrelated bit-streams (e.g., multiplication). Fig. 2 exemplifies these mappings.

Figure 2: Basic arithmetic operations in SC using minimal logic gates, highlighting correlation requirements.

Recent works have focused on low-discrepancy or quasi-random generators to improve bit-stream quality and minimize area/power overheads [Najafi_TVLSI_2019]. However, prior designs frequently relied on serial bit-stream processing limiting throughput. The architecture here eliminates serialization by organizing deterministic bit-stream mapping directly in memory arrays, leveraging spatial parallelism.

Universal Transcendental Function Implementation

Transcendental functions (e.g., $\sin(\cdot)$, $\cos(\cdot)$, $\exp(\cdot)$, $\ln(\cdot)$, $\tanh(\cdot)$) are critical to signal processing and ML, yet hardware implementations are traditionally costly (multi-cycle, wide datapath). The architecture decomposes these operators into cascades of SC primitives (AND/NAND), implementing truncated Maclaurin-series expansions as combinational LIM chains (Fig. 3).

Figure 3: Transcendental function library realized in stochastic logic for combinatorial, array-parallel evaluation.

This design supports scalable in-memory transcendental function computation without delay elements, contrasting with previous delay-FF-based SC circuits [Trig-Parhi]. The parallel combinational logic is readily mapped onto LIM structures, enabling SIMD execution across memory rows.

MTJ-Based Logic-in-Memory Structures and Architecture

The architecture is built on MTJ memory cells capable of nonvolatile storage and direct logic evaluation. The LIM cell structure (Fig. 4) orchestrates write/read phases: input operands are written as magnetic states; logic functions are evaluated via sense amplifier-based resistance comparisons.

Figure 4: Logic-in-memory cell integrating MTJ devices and CMOS peripherals for computation within memory arrays.

The full pipeline (Fig. 5) encompasses memory read, deterministic bit-stream mapping, parallel SCU-in-memory computation, and optional binary reconversion with bit-parallel summing mechanisms.

Figure 5: General overview of parallel in-memory stochastic architecture combining storage, conversion, and array-parallel computation.

MTJ cell operation (Fig. 6) supports row-level parallel access, essential for wide data-path stochastic processing.

Figure 6: MTJ memory cell operation: separate paths for write and read enable parallel, non-disruptive access.

In-memory deterministic bit-stream generation is realized via mapping binary bits using low-discrepancy patterns (Fig. 7), permitting both correlated and uncorrelated stream construction as required for SC arithmetic.

Figure 7: Deterministic pattern-based bit-stream generation from binary values in MTJ arrays.

Parallel SCU: Spatial SIMD Transformation

The SCU unit executes operations on spatial bit bundles rather than temporally. All $N$ bits of a stochastic operand undergo logic evaluation simultaneously (Fig. 8). Parallelism reduces computational latency for $N$-bit streams from $\mathcal{O}(N)$ cycles (serial) to $\mathcal{O}(1)$ (parallel).

Figure 8: SCU transformation—serial versus spatial parallel computation in memory.

The array executes arithmetic and transcendental functions via a spatially unrolled LIM instruction sequence. XOR/AND logic for binary conversion is realized directly in the memory peripheral (Fig. 9).

Figure 9: Parallel bit-stream-to-binary conversion in the LIM array.

This parallelism leverages available memory bandwidth and is scalable; hardware resources, sensing, and interconnects are traded for latency reduction.

Experimental Evaluation

Extensive simulation quantifies latency, power, fault tolerance, and accuracy. The architecture delivers a $22\times$–$\cos(\cdot)$0 speedup over serial SC, and latency improvements exceeding three orders of magnitude versus prior bit-serial IMC approaches. Accuracy is tunable via bit-stream length, and robustness is far superior to binary arithmetic under induced noise—error increases gradually rather than catastrophically at high error rates.

Processing-in-memory parallel image processing (PIM-PIM) is benchmarked with tone-mapping workloads. Deterministic parallel streams track reference tone curves with higher PSNR and lower MAE compared to random bit-stream implementations, confirming quantitative output fidelity (Fig. 10).

Figure 10: PIM-PIM in-memory tone-mapping using deterministic versus random bit-streams—deterministic output closely matches reference and achieves superior quality metrics.

Throughput and energy-delay product are significantly improved, with parallel SCU outperforming serial approaches in complex workloads at scale.

Implications, Applications, and Theoretical Outlook

This architecture conclusively demonstrates that integrating deterministic stochastic logic and combinational transcendental circuits within MTJ-based memories is a viable method to maximize memory-level parallelism. It substantially alleviates bandwidth and latency bottlenecks for SC-intensive and transcendental workloads, offering inherent fault tolerance and accuracy scalability—properties beneficial for approximate computing, neuromorphic systems, and large-scale data analytics.

Future research may explore further specialization for division and stateful operators, hierarchical scaling across multi-bank arrays, integration with hybrid memories, and direct mapping to vectorized learning architectures (e.g., in hyperdimensional computing [Kazemi2022], [RAHIMI2020195]). Additionally, hardware-software co-design for progressive precision trade-offs and adaptive accuracy control will be essential for workload-specific optimizations.

Conclusion

The proposed MTJ-based, deterministic parallel stochastic logic-in-memory architecture achieves substantial performance and energy advantages for arithmetic and transcendental operations, outperforming prior serial SC and IMC designs. By tightly coupling storage, conversion, computation, and write-back within LIM-enabled arrays, this work establishes a scalable pathway for throughput-oriented, reliable, low-latency computation in emerging AI and data-intensive applications.