Toward designing workload-aware Surface Code Architectures

Abstract: Practical quantum advantage is expected to depend on fault-tolerant quantum computing, although the architectural overhead needed to support fault tolerance is still extremely high. Prior FTQC designs generally emphasize either fast logical-qubit accessibility at the cost of significant qubit overhead, or high logical-qubit density at the cost of added workload latency. We propose an architecture that balances these competing objectives by placing surface-code patches around an ancilla-centric region, which yields nearly uniform ancilla access for all data qubits. Building on this design, we introduce a new workload-driven placement method that uses the $T$-gate profile of an application to determine an effective floorplan. We further provide a reconfigurable optimization for reducing the latency of $Y$-gate measurements on a per-workload basis. To improve flexibility, we also study concurrent execution of multiple programs on the same architecture. Numerical evaluation indicates that our approach keeps cycles per instruction near the optimal regime while reducing the number of required data tiles by up to $\sim21\%$, and achieves up to $\sim90\%$ efficiency when running 10 programs concurrently.

• The paper introduces a workload-aware surface code architecture that strategically maps T-gate heavy qubits to inner rings to minimize routing latency.
• It employs an annular floorplan with movement primitives and cost-driven qubit placement to preserve data tile density while reducing spatial overhead.
• Benchmarking demonstrates up to 3.86× lower cycles per T-gate and a 21% reduction in tile count, supporting efficient multiprogramming and fair resource sharing.

Toward Designing Workload-Aware Surface Code Architectures: An Expert Analysis

Introduction and Motivation

Surface code-based fault-tolerant quantum computing (FTQC) defines the practical scaling roadmap for quantum computation under realistic hardware constraints. However, such FTQC architectures impose tremendous overheads in terms of both space (physical qubits) and time (execution latency), driven by the need for robust error correction, magic-state distillation, and the intricate topology of lattice surgery. Most prior work on surface-code layout either maximizes data patch density at the expense of contention-induced latency or reserves excessive ancilla area for fast interactions, thereby inflating the qubit cost. This work, "Toward designing workload-aware Surface Code Architectures" (2604.19855), rigorously addresses these trade-offs by proposing a floorplan and resource mapping methodology that is explicitly optimized for the non-Clifford ($T$-gate) profile and interaction structure of quantum workloads. The architecture is also reconfigurable, supporting concurrent multiprogramming with quantifiable fairness and efficiency.

Architectural Landscape and Comparative Analysis

Previous designs along the density–latency trade-off curve include sparse layouts that ensure constant-time access to ancilla but dilute data tile density, and highly packed layouts that minimize spatial overhead but yield variable and often prohibitive routing costs.

Figure 1: Comparative summary of prior surface-code floorplans; data tile density declines as latency improves, illustrating the central trade-off.

Conventional designs such as "Fast Block" [Litinski_2019] prioritize short critical paths for arbitrary logical-qubit interactions (notably for high-frequency magic-state consumption), but at major cost in logical tile count and hence total physical qubits. On the other hand, high-density memory-focused architectures, exemplified by LSQCA, minimize resource overhead while sacrificing rapid interaction. These architectures generally neglect both workload heterogeneity (e.g., $T$-density and multi-qubit gate structure) and pragmatic multiprogramming requirements.

Annular, Workload-Aware Floorplan Design

The proposed stacked-annulus architecture organizes data tiles in concentric rings encircling a central compute region (CR) dedicated to ancilla and magic state distillation. This annular geometry confers several fundamental advantages:

1. Uniform and Bounded Latency: For innermost data tiles, movement to adjacent compute resources incurs a constant $O(1)$ time, while outer rings scale linearly with ring count, $O(L)$, but with bounded worst-case path length.
2. Density Preservation: By stacking additional rings outward, data tile density is maintained even with increasing workload sizes, and area occupancy scales sublinearly relative to alternatives.
3. Resource Partitioning: The architecture supports explicit partitioning of compute and data tiles, essential for efficient multiprogramming.

   Figure 2: The annular baseline, extended via outer data rings, with explicit entry points for magic state injection and highlight of workload-sensitive placement and fast-$Y$ optimizations.

Movement Primitives and Directed Annular Movement (DAM)

To minimize routing-induced latency, movement of logical patches utilizes three canonical primitives:

• Tangential Shift: Circular movement on a fixed ring,
• Radial Hop: Inward movement towards the compute region,
• CR Entry: Direct admission to a compute slot when at preferred angular locations.

This DAM protocol is orchestrated so that $T$-gate heavy qubits are mapped as close to CR entries as possible, minimizing both radial and angular distance.

Figure 3: Ancilla-assisted corner patch move enabling basis measurements despite geometric boundary constraints.

Figure 4: Visual depiction of tangential shift, radial hop, and CR entry; these constitute the movement primitives for patch scheduling.

Stacking outer rings improves peak density for large workloads (e.g., for QFT-128, density increases from $11.93\%$ to $84.7\%$ and total tile count drops by $\sim75\%$), at the expense of minor latency increases for the fraction of qubits located at the system periphery.

Figure 5: Analytical scaling of data tile density with grid size and ring stacking, empirically demonstrating dramatic reduction in floorplan requirements for large-instance QFT.

Workload-Aware Placement and Adaptive Optimization

The core placement algorithm leverages per-logical-qubit statistics—in particular, counts of single- and multi-qubit $T$ and $T$0 gates and their inter-qubit interaction degrees. A unified cost metric for each qubit determines a globally optimal location assignment: highest-cost (most $T$1/$T$2-dominated) qubits inhabit inner rings and preferred CR entry points, with movement pressure, $T$3-weighting, and $T$4-gate weighting as tunable parameters.

Figure 6: Cost-driven placement policy showing how qubits with dense $T$5/$T$6-profiles and multi-qubit interactions are prioritized for inner ring proximity to minimize long-path routing.

A further optimization, "fast-$T$7," deploys a selective two-tile encoding for specific high-frequency $T$8-gate qubits, permitting their measurement in a single cycle at the cost of modest tile overhead. The selection of qubits for this promotion is governed by a scoring function that balances expected time savings against displacement costs for other qubits.

Figure 7: Promotion of $T$9-basis measurement to fast path; top: unoptimized 5-cycle path, bottom: single-cycle at minimal tile cost.

Supporting Concurrency: Mapping, Fairness, and Scheduling

The architecture explicitly supports concurrent execution of multiple independent programs by partitioning compute-region and data ring capacity among workloads. Ring 0 and fast-$O(1)$0 allocations are distributed using quotas proportional to expected workload intensity and $O(1)$1/$O(1)$2 pressure, ensuring both throughput and per-job fairness.

Figure 8: Multi-workload concurrent execution and summary statistics including slowdown, system efficiency, and Jain’s fairness index.

Performance Characterization

Extensive benchmarking is performed using molecular Hamiltonians, arithmetic circuits (QFT, adders, multipliers), and custom $O(1)$3-gate–dense random circuits.

Figure 9: $O(1)$4 (code cycles per $O(1)$5-gate) spans across workloads, increases only weakly with stacking of outer rings; routing inflation remains modest even for high ring counts.

Key results include:

• Cycles per Instruction ($O(1)$6): For most practical workloads, $O(1)$7 is nearly flat as outer ring count increases. Proposed design achieves up to $O(1)$8 lower $O(1)$9 than prior density-optimized layouts, approaching the fast block limit but at vastly reduced tile overhead.
• Data Tile Requirement: The architecture reduces tile count by up to $O(L)$0 compared to non-latency-optimized dense layouts for arithmetic circuits.
• Measurement Optimization: Enabling fast-$O(L)$1 reduces measurement time by an average factor of $O(L)$2 and overall $O(L)$3 by $O(L)$4 for $O(L)$5-intensive workloads.

  Figure 10: Hyperparameter and ablation studies indicating that multi-qubit interaction degree dominates performance sensitivity, and that optimal cost balancing further improves placement efficiency and concurrency metrics.

• Resource Sharing Efficiency: Ten-way concurrent execution achieves $O(L)$6–$O(L)$7 efficiency, mean slowdown of $O(L)$8, and Jain’s index $O(L)$9, outperforming random or naïve multiprogramming policies.

Theoretical and Practical Implications

The results demonstrate that significant reductions in space-time overhead for FTQC are attainable via architectural codesign that is aware of workload structure—not only the aggregate $Y$0-count, but also the spatial pattern and multi-qubit interaction of non-Clifford gates. The design’s flexible ring stacking, cost-greedy placement, and localized measurement acceleration adapt readily to arbitrary quantum programs, minimize hardware budget, and maintain fairness under multiprogram workloads.

Further, the study sets the groundwork for practical deployment as quantum hardware reaches scales needed for realistic FTQC architectures. The reconfigurable floorplan, movement primitives, and scheduling policies are composable with emerging ideas in magic-state factory optimization, syndrome decoding, and inter-code heterogeneity (e.g., integrating with qLDPC memory and other subsystem codes).

Conclusion

This work provides a comprehensive, quantitative approach to surface-code architecture design under realistic FTQC constraints. By exploiting workload-aware placement, optimally scheduling movement, and selectively deploying fast measurement channels, it traces the Pareto frontier for data tile density versus execution time. The methodology’s support for multiprogramming, together with its bounded and tunable resource allocation, constitutes a significant step toward scalable, general-purpose quantum computing hardware. Future directions include its integration with hybrid code layouts, self-adapting placement for dynamically generated workloads, and detailed co-design with physical-level error models.

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Reference:

"Toward designing workload-aware Surface Code Architectures" (2604.19855)