- The paper develops a heuristic approach, combining release-aware DAG scheduling and one-step rollout sensing, mitigating delays and outlining when cross-stage parallelism improves timing.
- Joint scheduling, which enables start of DNN branch execution upon each radar band completion, achieves latency reductions exceeding 18% in initially sensing-constrained, heterogeneous setups.
- The results layout system performance varying from masterly alignment in sensing-constrained scenarios to potential regressions as core count increases or band heterogeneity decreases, which drives the need for more robust scheduling methodologies.
Motivation and problem setting
This paper addresses a coupling that is largely absent from both the radar-sensing and accelerator-scheduling literatures: when a multi-band radar feeds a multi-branch DNN, the completion time of each band's sensing determines the release time of that band's inference branch, so end-to-end latency depends jointly on band activation order and DAG execution on the accelerator (2604.18520). Conventional designs treat sensing and inference as strictly sequential stages: all bands must finish before inference begins, forfeiting any opportunity to overlap branch computation with ongoing sensing. The authors formulate a joint scheduling problem over (i) time-division band activation under time-varying SINR feasibility, (ii) non-preemptive job-to-core assignment on a C-core accelerator, and (iii) start/finish times subject to DAG precedence, with the objective of minimizing the makespan maxvfv.
The system model captures two effects often abstracted away elsewhere. First, sensing follows an information-accumulation model where each activated slot adds gk(γk(t))=Bklog(1+γk(t)) units toward a per-band threshold ηk, and only bands whose instantaneous SINR exceeds a threshold are eligible. Second, job latency is mapping-dependent: on-chip data forwarding between dependent jobs is possible only if they share a core and branch; otherwise outputs spill to off-chip memory at substantially higher read/write cost. This creates an explicit locality-versus-concurrency tradeoff inside the scheduler.
Algorithmic approach
Solving the joint problem exactly is intractable: it is a mixed discrete optimization with strong temporal coupling, and decisions must be made causally since future SINR realizations are unknown. The proposed method therefore approximates it with a two-level heuristic:
- Release-aware greedy DAG scheduler (RADG): given release times, jobs are processed in topological order and assigned to the core yielding the earliest completion time, respecting precedence, core availability, and release constraints. One pass costs O(C(V+E)).
- One-step rollout sensing rule: at each slot, every feasible unfinished band is tentatively activated; if this completes a band's sensing, its entry-job release time is updated, RADG is re-run, and the band minimizing the estimated makespan is selected. Total complexity is O(TKC(V+E)) versus O(TK+C(V+E)) for the decoupled baseline.
The decoupled baseline allocates each slot to the feasible band with the largest residual information demand—a purely sensing-driven rule—and schedules the DAG only after all bands complete, releasing all entry jobs simultaneously at maxkτk. The comparison thus isolates precisely the value of release-awareness in the sensing policy.
Simulation findings
The evaluation uses K=6 bands feeding six branches (node counts [5,6,7,6,8,6]) merged through two alignment nodes and a fusion head, with maxvfv0 cores by default, node latencies uniform in maxvfv1 ms, and off-chip access costs roughly an order of magnitude above on-chip costs.
Three qualitative results emerge from the timeline analysis. Under joint scheduling, branch execution begins immediately upon band completion, whereas the baseline delays all entry nodes until the last band finishes. Joint scheduling also produces release patterns better aligned with core availability, because each sensing decision accounts for downstream makespan impact.
Quantitatively, the gains are regime-dependent rather than universal:
| Setting |
Best gain |
Regime |
| Heterogeneous thresholds, moderate data (maxvfv2) |
+13.07% |
Strongly coupled |
| Halved data sizes (maxvfv3) |
+18.16% |
Sensing-constrained |
| Mixed branch depths maxvfv4 (maxvfv5) |
+18.16% |
Staggered releases |
| Uniform slices maxvfv6 kB |
≤ +1.47% |
Weak heterogeneity |
| 5× data sizes, maxvfv7 |
−3.92% |
Decoupled wins |
| Reduced to 3 active slices, maxvfv8 |
−6.19% |
Decoupled wins |
Two patterns deserve emphasis. First, the largest improvements occur when slice heterogeneity is high and sensing is the binding constraint—the conditions under which staggered branch releases create exploitable overlap. Second, and notably, the paper does not claim uniform superiority: at large core counts or with few active slices, the greedy one-step rollout can be slightly outperformed by the simple backlog-driven baseline, indicating that abundant compute or weak cross-branch coupling shifts the bottleneck to global ordering effects that a one-step look-ahead cannot capture. Core scaling also saturates beyond roughly 4–6 cores, as the critical path migrates from per-core contention to alignment/fusion synchronization.
Limitations and open questions
The paper is explicit about several caveats. The rollout heuristic carries no performance guarantee relative to the optimal solution of the joint problem, and its one-step horizon means sensing decisions are myopic with respect to future SINR evolution—consistent with the observed losses at high core counts. The evaluation relies on synthetic SINR processes (uniform in maxvfv9 dB), randomly generated node latencies, and a single representative DAG topology, so the boundary between gain and loss regimes is characterized empirically rather than analytically. The mapping-dependent latency model assumes on-chip forwarding only within same-core, same-branch pairs, which may not reflect accelerator architectures with shared on-chip buffers across cores. Open questions include whether multi-step or learned look-ahead policies can eliminate the regressions observed in low-coupling regimes, and what analytical conditions on threshold heterogeneity and branch depth predict when release-aware scheduling strictly dominates.
Conclusion
The paper contributes a unified timing model linking radar band completion to DNN branch release times, a tractable release-aware greedy scheduler exploiting this link, and a sensitivity analysis that delineates when cross-stage parallelism pays off. Latency reductions of up to approximately 18% are achieved in heterogeneous, sensing-constrained settings, while the honest reporting of cases where decoupled scheduling wins clarifies the operating envelope of the approach and motivates schedulers with stronger guarantees.