Parity-unfolded distillation architecture for noise-biased platforms

Abstract: We introduce the parity-unfolded architecture, a fault-tolerant quantum computing scheme that relies on direct preparation and teleportation of small-angle rotations $ Z^{1/2^{k}}$ rather than approximating them with the conventional (Clifford + $T$) gate set. The architecture is enabled by efficient distillation of gates from an arbitrary level of the Clifford hierarchy, which we refer to as parity unfolding. With it, a state $|Z_k\rangle = Z^{1/2^{k}}|{+}\rangle$ can be prepared fault-tolerantly using $2^{k+3} + O(2^{k/2})$ biased-noise qubits on a planar chip with nearest-neighbour connectivity. For algorithms requiring native $Z^{1/2^{k}}$ gates, such as the Quantum Fourier Transform and phase estimation, the proposed scheme allows to reduce resource overheads for up to $k=7$, i.e., up to $T^{1/32}$. Furthermore, when used for the synthesis of arbitrary small-angle rotations, parity-unfolded distillation of ($T$ + $\sqrt{T}$) reduces the minimum achievable logical error rate by 43% while cutting the resource requirements by 26%, when compared to unfolded distillation of only the $T$ gate.