Graph-Based ECO and Patch Generation for High-Level Synthesis

Abstract: High-level synthesis (HLS) tools offer limited support for Engineering Change Orders (ECOs), making late-stage design modifications challenging and costly. This paper introduces a graph-based ECO methodology tailored for Google XLS. A Graph Edit Distance (GED) algorithm is used to detect structural differences between original and revised intermediate representations (IRs), which are then transformed into patch operations. A patch application mechanism is developed to enforce XLS IR constraints while preserving semantic correctness, together with a schedule constraining scheme that maintains the original pipeline registers. Experiments across several XLS designs demonstrate high structural reuse ratios, effective schedule preservation, and full functional correctness, highlighting the practicality of the approach for production HLS flows.

• The paper presents a graph-based ECO methodology using GED to generate minimal, patch-level IR edits within the Google XLS HLS flow.
• It achieves up to 95% structural reuse and 78-92% schedule preservation, ensuring efficiency and integrity in design modifications.
• The approach integrates with XLS pipelines to maintain functional correctness and proposes future enhancements via parallel and ML-driven graph matching.

Graph-Based ECO and Patch Generation for High-Level Synthesis: Methodology, Results, and Implications

Introduction

This work presents a comprehensive graph-based ECO methodology tailored specifically for high-level synthesis (HLS) flows through the Google XLS toolchain. Unlike traditional Register-Transfer Level (RTL) ECO techniques, which suffer from limited structural flexibility in HLS environments due to disruptive synthesis and optimization, the proposed approach leverages direct structural differencing at the intermediate representation (IR) level using Graph Edit Distance (GED) principles. The methodology computes minimal edit operations for transforming one IR graph to another, generates compact patches, and enforces semantic and scheduling correctness within XLS pipelines.

Graph Edit Distance-Based ECO for XLS IR

The core of the methodology is the utilization of GED algorithms—esp. the DF-GED variant implemented in NetworkX—for high-fidelity differencing between the original and modified XLS IR graphs. The IR is parsed into a MultiDiGraph representation, capturing complex dataflow dependencies and operation attributes. Customized cost functions penalize structurally infeasible substitutions and guide the GED algorithm toward minimal edit paths strictly respecting XLS semantic constraints.

Patch operations are hierarchically structured and exported as protobufs containing node and edge insertions, deletions, and substitutions. The patch applier module then carefully applies edit operations to the IR while maintaining design invariants, employing staged edge/node updates, dummy nodes as temporary stand-ins, and operation order dictionaries to maximize structural reuse and minimize disruption.

Figure 1: Illustration of IR patching: (a) original IR implementing ret = (a + b) * c; (b) patched IR implementing ret = a - (b * c); (c) patch operations generated by the diff tool.

XLS ECO Flow and Schedule Preservation

The ECO flow fully integrates with Google XLS's build pipeline. The diff tool computes IR differences, generates patch instructions, and applies them to produce a structurally updated IR. A dedicated schedule-constraining mechanism then ensures that cycle-level timing and pipeline register alignment are preserved for common nodes, maintaining RTL similarity and minimizing downstream equivalence checking effort.

Figure 2: Overview of the XLS ECO Flow. Components with bold borders represent the proposed modules that are integrated into the original XLS flow.

The patch format is encapsulated in a hierarchical protobuf structure, distinguishing node and edge-level operations and their metadata.

Figure 3: Hierarchical structure of the patch protobuf.

Numerical Results and Structural Reuse

Evaluation on seven XLS designs spanning a range of complexities (CRC32, ZSTD Frame Decoder, ApFloat MAC, Simple RISCV, FIR Filter, Histogram, Vector Core) demonstrates the efficacy of the approach:

• Structural reuse ratios reach up to 95%, indicating that most nodes and edges remain intact across ECOs, with only minimal additions and deletions required even for substantial functional changes.
• Schedule preservation ratios range from 78% to 92%, confirming that the cycle-level timing constraints are retained for most pipeline elements.
• Functional correctness is fully verified for function-based designs at IR and RTL levels using XLS's Z3-based checker and Cadence Conformal LEC; proc-based designs are more challenging due to complex scheduling but mostly pass equivalence checks.
• Scalability limits are exposed: Non-linear growth in patch generation time and peak RAM usage is observed for larger designs, with some cases requiring over an hour and tens of GBs.

  Figure 4: Fraction of reuse (substitutions and unchanged structure) versus structural modification (insertions and deletions) across all evaluated designs. Bars are normalized to total edit operations.

Resource Consumption and Limitations

Resource analysis demonstrates that small designs require <1GB RAM and complete in less than one minute while large designs demand substantial memory and compute overhead, stressing the scalability of NetworkX GED and the need for parallelization.

Schedule Preservation Metrics

Detailed analysis shows the methodology achieves high preservation of original schedule constraints except in cases of infeasible nodes or newly inserted elements. Runtime for schedule constraint resolution also increases with design complexity.

Implications and Future Directions

The graph-based ECO methodology directly addresses the need for fine-grained IR-level patching in modern HLS toolchains, enabling late-stage modifications that are structurally minimal and semantically robust. The high reuse ratios and effective schedule preservation translate to practical benefits in maintaining pipeline timing, register naming, and RTL equivalence, results not achievable by traditional string or operator-level differencing. This supports improved incremental compilation, stabile physical design, and reduced verification complexity in ASIC flows.

The current limits of GED performance highlight opportunities for further research—multithreaded graph matching, ML-driven edit path prediction, and automated equivalence checking for intricate stateful designs. Integration of ML methods, as discussed in the paper, may improve both the speed and accuracy of graph matching, especially for large-scale IRs. Additional robustness in verification, especially for proc-based designs, remains an open challenge.

Conclusion

The presented graph-based ECO methodology for high-level synthesis through XLS demonstrates robust structural reuse, effective schedule preservation, and full functional correctness with minimal disruption. The approach is fully open-source and integrable into production HLS flows, enabling practical, systematic late-stage hardware design modifications. Future advances are expected in scalability, automation, and verification, potentially leveraging parallel or ML-driven graph matching paradigms to further enhance ECO support in HLS environments.