Tunable Valley Polarization in Diamond

Abstract: Device stability is essential for quantum information technologies, where reliable control of electronic states is crucial. Diamond valleytronics offers a promising platform by exploiting the valley degree of freedom to store and manipulate information. In this work, we demonstrate a diamond-based valley transistor with a dual-gate, two-drain architecture that enables tunable valley-polarized transport via gate voltage modulation. By leveraging the significant effective-mass anisotropy of diamond's conduction band valleys, this architecture provides control over spatial distribution and transit times. We further demonstrate that valley-polarized transport in diamond is remarkably robust against thermal variations over macroscopic distances. These results demonstrate the resilience of valley states and highlight diamond's potential for energy-efficient valleytronic devices in next-generation quantum and high-power electronics.

• The paper demonstrates tunable valley polarization in diamond using a dual-gate transistor architecture that maintains valley coherence over macroscopic distances.
• It employs picosecond-scale photogeneration and time-resolved current readout to quantify intervalley scattering and drift dynamics over a 10–77 K temperature range.
• Results indicate robust device stability and thermal resilience, supporting scalable valleytronic logic and potential quantum integration.

Tunable Valley Polarization and Robust Valleytronics in Diamond

Introduction and Motivation

The exploitation of the valley degree of freedom in electrons, or valleytronics, is emerging as a robust paradigm for the manipulation of quantum information in semiconductors. While valley-based devices have been extensively explored in 2D materials with strong spin-orbit coupling (TMDs, graphene), the potential for bulk semiconductors—particularly diamond—remains under-explored. Diamond provides a unique combination of sixfold valley degeneracy, wide bandgap, high thermal conductivity, and high breakdown voltage, suited to high-power and quantum device applications.

Experimental Architecture and Methodology

The study details the design and characterization of a dual-gate, two-drain diamond-based valley transistor fabricated from high-purity CVD-grown single-crystal diamond with sub-ppb nitrogen concentration. A 30 nm Al₂O₃ gate dielectric is employed to ensure interface passivation and reduce trap densities. The device enables electrostatic manipulation via independently-addressable source, gates, and drains, facilitating spatial and temporal separation of valley-polarized electron populations generated by UV pulsed excitation.

Carrier dynamics are interrogated using picosecond-scale photogeneration and time-resolved induced current readout, ensuring that both drift, diffusion, and intervalley relaxation phenomena are quantifiable within sub-100 ns resolution. Devices are characterized over 10–77 K in high vacuum to disentangle phonon-mediated scattering from impurity- and interface-limited transport.

Fundamental Mechanisms of Valley-Polarized Transport

In diamond, the conduction band is characterized by pronounced effective-mass anisotropy, with a longitudinal mass $m_l$ ($\sim$1.56$m_0$) and a significantly lighter transverse mass $m_t$ ($\sim$0.28$m_0$). Intervalley scattering is strongly suppressed below room temperature due to high optical phonon energies of 110 meV (orthogonal valleys, f-type) and 165 meV (opposite valleys, g-type), vastly exceeding $k_BT$ in the measured temperature range. This suppression ensures that electron populations, once initialized in specific valleys, remain coherent over macroscopic drift distances, provided the experimental timescale is shorter than $\tau_{fg} \sim 300$ ns at 77 K.

Intravalley acoustic scattering, in contrast, dominates carrier mobility with a shorter timescale ($\sim$1 ps at 77 K) and significant inelasticity due to diamond’s high sound velocity and Debye temperature, invoking a deviation from the typical $T^{-3/2}$ dependence.

Device Operation, Electrostatic Valley Steering, and Spatial Separation

Systematic modulation of gate voltages enables both lateral (in-plane) and vertical (out-of-plane) electric fields within the diamond channel. Left-gate voltage primarily controls penetration depth by modulating the transverse field, selectively confining (001) valley electrons near the surface while allowing (100)/(010) valley populations to penetrate into the bulk. The right-gate bias acts as a spatial steering mechanism, dynamically partitioning valley populations between Drain 1 and Drain 2. The backplane provides additional vertical confinement, demonstrated to further restrict spatial separation and adjust collection efficiency.

Time-resolved measurements display clear and reproducible separation of valley-dependent current peaks at the nanosecond scale. Increasing left-gate voltage pushes the bulk-confined valleys away from the surface and modulates population overlap with each drain. The right-gate and backplane voltages independently tune the in-plane and out-of-plane distributions, providing orthogonal control and a versatile platform for valleytronic logic functionality.

Sample Reproducibility and Interface Effects

Comparison of nominally identical samples reveals minimal impact on core valley-dependent transport, with the exception of threshold shifts and current amplitude changes attributable to differences in interface trap densities and fixed charges in the Al₂O₃ layer. Despite device-specific variations in required gate voltage for peak steering, the qualitative and quantitative hallmarks (velocity differential, temporal separation, selectivity) of valley polarization remain robust, underscoring the reproducibility and universality of the described transport phenomena.

Repeat measurements on individual samples over week-long intervals display negligible drift in current signatures, confirming device and measurement stability.

Thermal Robustness and Temperature-Dependent Valley Transport

Carrier drift times are measured from 8.7 ns (10 K) to 21.6 ns (77 K), an increase by a factor of $\sim$02.5. This temperature dependence is attributed to enhanced acoustic phonon scattering; however, intervalley scattering remains largely inactive, and valley polarization persists across the full measurement range. Increased temperature leads to a broader and attenuated current peak, indicative of enhanced diffusion, but does not diminish the resolution of valley separation within experimental uncertainty. These results are consistent with vertical time-of-flight benchmarks and further establish the superiority of diamond for low-temperature valleytronics where long valley lifetimes are desirable.

Implications, Limitations, and Directions for Future Research

The demonstration of electrostatically-tunable, thermally-robust valley-polarized transport in diamond advances the implementation of logic and quantum information devices based on valley degree of freedom. The architecture described enables non-volatile, low-power operation with inherent resilience against thermal noise, interface scattering, and sample variability—critical attributes for scalable quantum and classical hybrid platforms.

The method provides a practical pathway towards energy-efficient valleytronic logic gates, transistors, and quantum node interconnects, with potential extensions to optically-addressable NV centers for integrated quantum-classical operations. Open questions remain regarding higher-temperature operation, integration with existing CMOS process flows, and the ultimate limits of valley coherence under strong electric, thermal, and optical perturbation.

Conclusion

This work establishes a tunable, dual-gate diamond valley transistor platform exhibiting reproducible and robust valley polarization over distances applicable to real-world devices. The findings support the deployment of diamond for valley-based classical and quantum devices, leveraging its stability, anisotropy, and thermal management advantages. Future efforts should target integration with scalable device topologies, investigation of room-temperature operation through dynamic valley locking or resonant excitation, and hybridization with spin defects for coherent quantum information processing.