PHAROS: Pipelined Heterogeneous Accelerators for Real-time Safety-critical Systems With Deadline Compliance

Abstract: Spatially partitioned heterogeneous accelerators (HAs) are increasingly adopted in embedded systems for their performance and flexibility. Yet most existing HA design frameworks optimize primarily for throughput or quality-of-service (QoS) metrics. They often overlook safety-critical real-time requirements, including hardware support for predictable execution, real-time-aware design space exploration (DSE), and rigorous schedulability analysis. These requirements are essential in safety-critical applications such as smart transportation, where schedulability guarantees directly affect system safety. To address this gap, we present PHAROS, a real-time-centric HA design framework. PHAROS introduces preemption mechanisms and scheduler designs for spatially partitioned HAs under first-in-first-out (FIFO) and earliest-deadline-first (EDF) policies. Leveraging modern real-time theory, we further develop a soft real-time (SRT) schedulability-oriented DSE with objectives and constraints tailored to SRT schedulability. Through comprehensive modeling, analysis, and evaluation across diverse applications, we show that PHAROS's DSE discovers more feasible configurations for a broader range of task sets than throughput-oriented DSE baselines while delivering improved real-time performance. We also provide response-time analyses for the supported scheduling algorithms.

• The paper introduces a real-time scheduling framework that employs hardware preemption and formal response-time analysis to guarantee deadline compliance.
• It leverages a pipelined heterogeneous accelerator architecture with decentralized FIFO and EDF schedulers to robustly manage task workflows.
• The design space exploration using a beam search strategy significantly reduces search time while expanding feasible SRT-schedulable configurations compared to throughput-based approaches.

PHAROS: Pipelined Heterogeneous Accelerators for Real-time Safety-critical Systems With Deadline Compliance

Introduction and Motivation

The increasing adoption of spatially partitioned heterogeneous accelerators (HAs) in embedded systems is driven by requirements for both performance and flexibility, particularly in domains such as smart transportation where deadline compliance is critical. Despite the utilization of HAs in such contexts, prevailing design frameworks overwhelmingly prioritize throughput or quality-of-service (QoS), and neglect the strict requirements found in real-time safety-critical systems—particularly hardware support for predictable execution, comprehensive real-time design space exploration (DSE), and formal schedulability analysis. The paper "PHAROS: Pipelined Heterogeneous Accelerators for Real-time Safety-critical Systems With Deadline Compliance" (2604.05308), directly addresses these gaps by defining a real-time-centric HA framework and co-designing hardware mechanisms for preemption with formal soft real-time (SRT) schedulability guarantees.

The PHAROS framework introduces key innovations: hardware support for efficient preemption (both at the tile and layer levels), dynamic on-chip scheduling (FIFO and EDF), explicit incorporation of real-time scheduling theory for DSE, and formalized response-time analysis. The central claim is that schedulability-oriented DSEs, as realized by PHAROS, yield significantly more feasible real-time taskset configurations and improved utilization than traditional throughput-oriented methods.

PHAROS Architecture and Preemption Support

PHAROS defines an architecture comprising multiple independent dataflow accelerators, each managed by a decentralized scheduler. The overall design is engineered to be compatible with both FIFO and EDF scheduling paradigms, including hardware-level preemption support. Each accelerator contains a static configuration table, a dynamic progress table, and a per-task job pool. Layer assignments, on-chip/inter-accelerator communication, and DDR allocation are statically determined to guarantee memory isolation.

Figure 1: The hardware organization of the PHAROS system with decentralized on-chip schedulers, memory partitioning, and double-buffered DMA engines.

Preemption granularity is managed at the tile level, leveraging the output-stationary dataflow paradigm. When a higher-priority job arrives, the accelerator completes the current tile, persists partial results, and records progress before context switching. This approach bounds preemption overhead as a function of tile size, DMA latency, and load/store times, all of which are formally modeled in schedulability analysis.

Figure 2: Preemption events are handled at tile boundaries, and all latencies for storing/loading context are explicitly modeled.

Taskset Modeling and Real-time Theory Application

Tasksets are specified as sequences of DNN layers for each periodic or sporadic job. The system is modeled as a pipeline of $M$ accelerators; each task is decomposed into segments mapped to accelerators according to a non-backtracking, pipelined topology. Following [dong2017optimal], the condition for SRT schedulability is that the utilization $u^k = \sum_i (e_i^k / p_i)$ on each accelerator must not exceed 1. Critically, preemption overheads are included in the modeled worst-case execution times ($e_i^k = b_i^k + \xi_i^k$).

This modeling enables PHAROS to directly leverage theoretical guarantees for SRT systems, notably that SRT deadline compliance is achieved if and only if per-accelerator utilization is below unity for both FIFO and EDF, provided all hardware-level preemption effects are accounted for.

Schedulability-driven Design Space Exploration

PHAROS fundamentally recasts DSE for HAs as a schedulability-constrained optimization, moving away from throughput-centric objectives. The DSE procedure determines how platform resources are partitioned, how layers are topologically assigned to accelerators, and how architectural parameters (e.g., PE array sizes, tiling) are selected.

Rather than maximizing throughput, the DSE seeks to minimize the maximum accelerator utilization, effectively maximizing the feasible task workload space under SRT compliance. The large design space is managed by a novel beam search strategy, with proven pruning and branching logic supporting rapid convergence to near-optimal configurations even as the number of tasks and layers increases.

Figure 3: The PHAROS DSE explores partitioning and mapping options under strict resource, pipeline, and utilization constraints.

Figure 4: Visualization of beam search progress, illustrating iterative branching, pruning, and accumulation of feasible partition/mapping strategies.

The practicality and scalability of the DSE approach are supported by results showing exponential savings in search time without significant loss of solution quality relative to brute-force enumeration.

Experimental Results

SRT-Schedulability and Utility Gains

PHAROS is evaluated across diverse combinations of real-world DNN models with over 100 synthesized tasksets per combination. Schedulability-guided (SG) and throughput-guided (TG) DSE approaches are systematically compared under both FIFO and EDF scheduling.

PHAROS's SG-DSE identifies up to 2.28$\times$ more SRT-schedulable taskset configurations compared to TG-DSE. For challenging application mixes, the SRT-feasible design space is expanded by up to 3.76$\times$, directly correlating with enhanced system robustness and allowable task rates in practical deployments.

Figure 5: Schedulability of various DSE methodologies on PointNet/Bert-B mixtures; PHAROS greatly expands the feasible region.

Figure 6: SRT-schedulability comparison for PointNet/Bert-S workloads, demonstrating a broader range of safe operating points for PHAROS.

Figure 7: Analysis of SRT-feasible design points for both SG and TG DSEs under FIFO and EDF, highlighting PHAROS’s dominance.

Maximum Utilization and Accelerator Efficiency

PHAROS also demonstrates up to 6.2% tighter maximum utilization compared with throughput-optimized designs, and across most application mixes the PHAROS configurations yield lower or comparable utilization even when subjected to stringent period constraints.

Figure 8: Maximum accelerator utilization queried across period setups for PointNet-ResMLP, revealing efficiency improvements with SRT-guided design.

Scheduler Performance and Policy Tradeoffs

PHAROS supports both FIFO and EDF, with explicit response-time analysis for both. Simulations indicate that EDF can yield superior latency outcomes, especially when there is significant variability in task rates and execution times. However, EDF introduces preemption overhead; thus, its benefits are workload dependent.

Figure 9: Response time distributions for FIFO and EDF scheduling on representative application pairs; EDF yields lower means for high-variance workload mixes.

Search Efficiency

The beam search heuristic reduces DSE times by over two orders of magnitude versus brute-force without compromising solution quality, and supports rapid first-feasible discovery for practical co-design flows.

Figure 10: Comparative search durations: beam search achieves near-optimal results exponentially faster than brute-force in PointNet-DeiT-T scenarios.

Implications and Future Directions

PHAROS demonstrates that formal real-time theory can—when embedded into hardware/software DSE and supported by robust preemption/scheduling mechanisms—substantially widen the effective design space for safety-critical HA systems. This has direct impact on the deployability of DNN-centric embedded platforms in applications such as perception, planning, and sensor fusion within cyber-physical systems, where SRT (or HRT) guarantee violations can be catastrophic.

While PHAROS centers on pipelined topologies (limiting flexibility for arbitrarily-structured DAGs), the empirical coverage of spatial accelerator designs is shown to be broad. Future work includes extending real-time theoretic analysis to more general HA interconnects and exploiting more granular layer/data parallelism within and across tasks.

Conclusion

The PHAROS framework introduces an SRT-centric, schedulability-driven design methodology for heterogeneous accelerators, encompassing both hardware and system-level innovations. By integrating formal real-time schedulability conditions, fast DSE, and hardware-level EDF/FIFO preemption, PHAROS achieves significantly greater practical SRT taskset coverage and higher hardware efficiency than throughput-centric baselines. These results substantiate the necessity of co-designing accelerator architectures, runtime scheduling, and DSE under mathematically rigorous real-time constraints to enable robust deployment of DNN workloads in modern safety-critical systems.