The Eleventh NTIRE 2026 Efficient Super-Resolution Challenge Report

Abstract: This paper reviews the NTIRE 2026 challenge on efficient single-image super-resolution with a focus on the proposed solutions and results. The aim of this challenge is to devise a network that reduces one or several aspects, such as runtime, parameters, and FLOPs, while maintaining PSNR of around 26.90 dB on the DIV2K_LSDIR_valid dataset, and 26.99 dB on the DIV2K_LSDIR_test dataset. The challenge had 95 registered participants, and 15 teams made valid submissions. They gauge the state-of-the-art results for efficient single-image super-resolution.

• The paper introduces a benchmark for efficient super-resolution that prioritizes runtime over traditional quality metrics.
• The winning SPANV2 model leverages hardware-software co-design with fused CUDA kernels and parameter-free attention to achieve a 5.26 ms runtime.
• The challenge reveals an efficiency paradox, emphasizing structured pruning, knowledge distillation, and operator fusion for practical deployment.

The Eleventh NTIRE 2026 Efficient Super-Resolution Challenge: Technical Summary and Analysis

Introduction and Scope

The Eleventh NTIRE 2026 Efficient Super-Resolution Challenge establishes a comprehensive benchmark for state-of-the-art, efficiency-centric single image super-resolution (SR) methods. Unlike traditional SR competitions emphasizing peak signal-to-noise ratio (PSNR) alone, this challenge makes runtime the principal criterion, while still requiring fidelity quality (PSNR ≥ 26.99 dB on DIV2K_LSDIR_test, 26.90 dB on DIV2K_LSDIR_valid). Efficiency is measured multidimensionally: runtime, parameter count, and floating-point operations (FLOPs). This multi-metric focus reflects practical deployment targets, where latency, memory, and compute constraints are critical—especially for real-world applications in mobile and edge devices.

The challenge is staged on the DIV2K and LSDIR datasets with strict evaluation: only models meeting the minimum PSNR are ranked, and a new scoring function gives runtime a dominant 0.8 weight, emphasizing real inference speed over raw arithmetic complexity.

Challenge Protocol and Evaluation Criteria

Participants were provided with high-diversity training pairs and restricted from using validation or test images for training. Runtime was computed as the mean inference time (on an NVIDIA RTX A6000) on the union of DIV2K and LSDIR validation and test images. FLOPs were measured for $256\times256$ input. The scoring formula combines runtime (dominant), parameters, and FLOPs into a composite “significance” score, focusing on methods excelling in real-time, low-complexity deployment rather than exclusively theoretical calculation efficiency.

Technical Innovations and Methodological Trends

Hardware-Aware Optimization and Operator Fusion

A defining result is the emergence of hardware-software co-design. The winning solution, SPANV2 by XiaomiMM, exemplifies this, demonstrating that for compact CNNs, memory bandwidth—not multiply–accumulate (MAC) throughput—dominates runtime. The SPANV2 architecture innovates through:

• Parameter-free Attention Redesign: Core attention blocks are enhanced from element-wise multiplication of static intermediate features to learned $1\times1$ projections, enabling content-adaptive, cross-channel mixing with negligible parameter overhead.
• span_attn_op Fused CUDA Kernel: The attention computation (convolution, add, multiply) is executed in a single custom CUDA kernel, reducing DRAM access by 3× and eliminating memory round-trips that typically throttle arithmetic efficiency.

  Figure 1: SPANV2 overall architecture, combining a near-pixel upsampling branch and five SPABV2 blocks for feature extraction.

  

  Figure 2: The span_attn_op CUDA kernel fuses convolutions and elementwise ops, directly targeting memory bandwidth bottlenecks.

• Near-pixel Upsampling Branch: A parallel depthwise path initialized as nearest-neighbor upsampling leverages natural image low-frequency priors, allowing deep layers to focus on residual refinement rather than global reconstruction.

These systems-level optimizations bring SPANV2 to 0.139M parameters, 9.11G FLOPs, and an average runtime of 5.26 ms, setting a new standard for hardware-aware efficiency.

Structured Model Compression

A major trend is the convergence of pruning and distillation for deep neural network compression. Teams such as BOE_AIoT and PKDSR prune channel counts in strong backbones (e.g., SPANF) in multi-stage protocols, each followed by distillation: the pruned “student” is tuned under supervision from a full “teacher,” mitigating reconstruction degradation due to aggressive parameter reduction. PKDSR's two-stage pruning (32→28→24 channels) demonstrates stable PSNR with minimal quality loss, confirming the reliability and practicality of this approach.

Knowledge Distillation and Attention/Context Enhancement

Distillation is generalized beyond pruning: VARH-AI employs DSCLoRA, a multi-head separable convolution LoRA block with spatial affinity alignment, and custom MuAdamW optimization for stability and convergence. Cross-block knowledge transfer and frequency-aware auxiliary losses are widely practiced, as observed in VARH-AI and WMESR.

Structural Re-Parameterization

Several entries, including Just Try (ERRN2) and DISP, leverage multi-branch training-time architectural designs which collapse to single-convolution modules at inference—structurally re-parameterizing for zero extra inference cost. Exact operator fusion, as in VARH-AI, mathematically combines cascaded convolutions into higher-order kernels (e.g., $5\times5$), further stripping parameters and boosting efficiency.

State Space Models (Mamba) and Frequency Decoupling

Two teams (e.g., CUIT_HTT with MambaGate-SR, WMESR with DWMamba) explore incorporation of efficient state space models (specifically Mamba modules) for better context aggregation. DWMamba decomposes features via Haar wavelet, handles LL subbands (global context) with MambaIRv2, and processes high-frequency channels with lightweight CNN followed by cross-frequency gating.

Figure 3: DWMamba's frequency-decoupled architecture integrates wavelet domain state-space modeling and cross-frequency interaction.

This approach confirms Mamba’s potential for global modeling at reduced scale, though practical advantages in runtime remain limited relative to best CNNs.

Lightweight Spatial/Channel Attention and Multi-Scale Designs

HAESR demonstrates shared hybrid attention blocks, reusing maps generated in early layers for subsequent blocks—reducing redundancy in local-global enhancement, while VSCINet and HFENet further streamline spatial/channel interaction via variance-guided and entropy-driven blocks (Figures 8 and 7, respectively).

Figure 4: HFENet employs cascaded multi-scale attention and entropy-guided channel weighting for parameter-efficient context modeling.

Figure 5: VSCINet integrates variance-guided spatial attention, multi-scale convolutions, and efficient channel blocks for SR.

Quantitative Results and Observations

• Runtime Leadership: XiaomiMM’s SPANV2 achieves the lowest runtime (5.26 ms) with high efficiency and competitive PSNR, securing 1st in the main track. DISP and BOE_AIoT follow, all sub-7 ms.
• Minimum Model Footprint: ZenoSR and XuptSR achieve sub-0.05M parameters and ≤3.5G FLOPs, but at the cost of increased inference time (over 48 ms), illustrating the “efficiency paradox”: minimizing arithmetic complexity and parameters does not guarantee fast end-to-end runtime due to suboptimal operator scheduling and memory access patterns.
• Best Quantitative Quality: Teams such as HAESR (27.22 dB), WMESR (27.06 dB), and Sunflower/XuptSR (27.03 dB) lead in PSNR but with inflated inference time, reaffirming that this challenge does not reward absolute accuracy beyond the efficiency floor.

Core Themes and Contradictory Findings

• Efficiency Paradox: Top methods for minimal parameter count or FLOPs (e.g., ZenoSR, XuptSR) do not align with minimum runtime, indicating nontrivial hardware bottlenecks are the enduring limiting factor.
• Runtime Supremacy: The new scoring design amplifies runtime importance; the best runtime now nearly guarantees top overall ranking, motivating hardware/software codesign as the path forward.
• Emerging Hardware-Awareness: Custom CUDA kernels and fused operators prove critical in extracting maximum speed from memory-bound CNNs, even when conventional FLOPs count is not reduced.

Theoretical and Practical Implications

The sustained ability of the community to push image SR to new efficiency frontiers is evident, with 15 valid teams balancing the PSNR/efficiency tradeoff. The embrace of hardware-aware, operator-level fusions, and cross-disciplinary optimization (algorithm/compiler/hardware stack) suggests future research will focus on:

• Holistic Model–System Joint Design: Co-optimization of neural blocks (for fusion/compression) and kernel-level implementations tailored to deployment platforms (GPU/edge/ASIC).
• Generalized Knowledge Distillation: Broader applications in domain adaptation, low-precision quantization, and continual model compression.
• Efficient State Space and Frequency Approaches: Further refining context modeling with SSMs, especially for global–local dependency integration with bounded latency.
• Beyond Arithmetic Complexity: Rethinking benchmarks to emphasize real, observable inference speed—including activation footprints, batch latency, and throughput—over conventional model size metrics.

Conclusion

The Eleventh NTIRE 2026 Efficient Super-Resolution Challenge (2604.03198) exemplifies the maturation of efficient deep learning for practical SR deployment, substantiating that progress now critically depends on both architectural and system-level engineering. As SOTA methods now saturate algorithmic design space, future breakthroughs will arise from hardware-congruent computational patterns, fusing hardware, software, and machine learning advances into deeply collaborative efficient AI pipelines.