EEspice: A Modular Circuit Simulation Platform with Parallel Device Model Evaluation via Graph Coloring

Abstract: As modern analogue/mixed-signal design increasingly relies on optimization-in-the-loop flows, such as AI and LLM-based sizing agents that repeatedly invoke SPICE-efficient, accurate high-performance simulators have become an indispensable foundation for modern integrated circuit (IC) design. However, the computational cost of evaluating nonlinear models, particularly for BSIM models, remains a significant bottleneck. In standard parallelization approaches, devices such as transistors are easily distributed across processors. The subsequent stamping phase, where each device's contributions are added to the shared system matrix, often creates a bottleneck. Because multiple processor cores compete to update the same matrix elements simultaneously, the system is forced to process tasks one at a time to avoid errors. This paper introduces EEspice, an open-source circuit simulation framework whose modular architecture decouples device model evaluation into independently replaceable kernels, enabling a parallel stamping strategy that overcomes this bottleneck. It partitions MOSFET instances into independent color groups, which can be processed in parallel. Our results show that on a 64-core workstation, the proposed approach achieves up to 45x speedup over single-thread performance when conflicts are low. Our analysis also explores how performance depends on circuit topology.

• The paper demonstrates a novel graph coloring scheme that enables lock-free, parallel evaluation and stamping of device models in circuit simulation.
• It leverages a modular architecture with fused kernel strategies to significantly boost performance, showing speedups up to 45× over traditional methods.
• The work offers actionable insights for integrating EDA workflows with AI-driven design automation while maintaining bit-exact numerical accuracy.

EEspice: Graph Coloring-Based Parallel Circuit Simulation for Efficient Device Model Evaluation

Introduction

EEspice presents a modular circuit simulation platform engineered to address the scalability bottlenecks of traditional SPICE-like simulators in the context of modern analog/mixed-signal IC design. As design flows increasingly leverage optimization-in-the-loop paradigms and LLM-based sizing agents, the computational throughput requirements for transient simulation, especially for nonlinear compact models such as BSIM, are rising dramatically. The principal innovation in EEspice is the adoption of a graph coloring scheme to enable lock-free, parallel matrix stamping, directly addressing parallelization inefficiencies observed in conventional shared-memory implementations. This essay examines the methodology, numerical results, and implications for future EDA and AI-driven design automation.

Methodology and Architectural Innovations

EEspice adopts a modular architecture, encapsulating device evaluation and stamping within interchangeable kernel modules that allow for distinct parallelization strategies without core algorithmic alteration. The standard analysis loop—transient or DC—is decomposed into two phases per Newton–Raphson (NR) iteration: (i) embarrassingly parallel device evaluation, and (ii) the matrix stamping phase, wherein each device contributes to the global MNA system.

In traditional OpenMP-based approaches, parallelism is only applied in the device evaluation phase; stamping remains serial or lock-regulated, leading to severe contention bottlenecks. EEspice overcomes this by constructing a device conflict graph—where vertices represent device instances and edges denote shared circuit nodes—and then solving a coloring problem such that no two adjacent vertices share the same color. Devices of the same color are guaranteed to have disjoint stamping targets, enabling conflict-free parallel writes. Devices are partitioned into color sets, and stamping-evaluation within each color is fused and executed in parallel, with colors processed sequentially—entirely eliminating the need for atomic locks or serialization.

Figure 1: Typical transient simulation flowchart highlighting the NR-based loop and the decoupled evaluation/stamping in EEspice.

Figure 2: Mapping of a 5-transistor OTA to a conflict graph, illustrating graph coloring-based partitioning for parallel stamping.

Four evaluation-stamping kernel strategies are supported:

• loadsingle: Naively sequential baseline.
• loadomp: OpenMP parallelized device evaluation but sequential stamping.
• Color: Graph coloring-based, parallel within each color for evaluation and stamping.
• ColorFused: Fused evaluation/stamping per device, parallel execution within each color.

Numerical Accuracy and Speedup Results

EEspice demonstrates bit-exact waveform agreement with Ngspice for both DC and transient invariants, confirming correctness independent of kernel choice or parallelization strategy.

Figure 3: Accuracy comparison versus Ngspice for BSIM4 DC characteristics and inverter transient responses.

The kernel microbenchmarks isolate device evaluation cost and clearly show that, under moderate to high device conflict, conventional OpenMP parallelization saturates at a maximal speedup of approximately $1.5\times$ due to stamping serialization. In contrast, graph coloring-based approaches (Color/ColorFused) remove this bottleneck, with observed speedups up to $4.4\times$ under moderate conflict, and up to $45\times$ in the absence of conflict. These results are topology-dependent: as the number of required colors ($C$) increases (higher device–node sharing), synchronization overheads reduce speedup, but circuits of larger device cardinality sustain parallel efficiency deeper into the high-$C$ regime.

Figure 4: BSIM4 evaluation time breakdown; parallel compute scales, but sequential stamping (loadomp) caps speedup, circumvented by coloring-based parallel stamping.

Figure 5: Speedup scaling with thread count and color count; large speedups in low-conflict, high-parallelism regimes, with diminishing returns as color fragmentation increases.

A full-system transient benchmark on a 64-bit ripple-carry adder reveals nuanced trade-offs: direct circuit topologies with high node-fan-in (large $C$) preferentially favor loadomp, while introducing series resistors to segment shared nodes (lower $C$) enables ColorFused to outperform all baselines. However, such modifications increase the size and sparsity of the global linear system, causing the matrix solve stage to become the new performance limiter once device evaluation is minimized.

Figure 6: Schematic of the 28-transistor full adder circuit used in transient benchmarks.

Figure 7: Transient simulation of the 64-bit adder; EEspice waveforms are virtually indistinguishable from Ngspice, with relative errors $<$1%.

Discussion and Implications

The strong dependence of parallel scaling on the device–node sharing induced color count ($C$) establishes an important theoretical-practical boundary for colored parallelization in device-centric simulators. For real-world topologies featuring clustered node sharing or heavy post-layout parasitics, the natural fragmentation of the conflict graph ensures that coloring remains effective, particularly for analog/rf and large digital blocks with sparse inter-device connectivity.

Numerical results underscore a paradigm shift: once device evaluation becomes efficiently parallelized and no longer bottlenecked by serialization, responsibility for runtime moves to the sparse linear solver. Thus, full-stack simulation performance on modern many-core architectures will require the integration of highly-optimized, circuit-structure aware sparse solvers (e.g., PARDISO, cuDSS), potentially co-designed with circuit partitioning or coloring approaches.

Practically, these findings have significant consequences for the deployment of AI/LLM-driven automated sizing, topological synthesis, and verification flows, where simulator throughput is critical for iterative, high-volume queries. The modularity of EEspice further positions it as a testbed for integrating emerging device models (e.g., BSIM-CMG FinFET), solver backends, and hardware-adaptive kernels.

Future Directions

Key research directions include:

• Integration of GPU/FPGA-resident evaluation kernels, extending coloring-based parallelization across heterogeneous computation substrates.
• Development of adaptive graph coloring and partitioning heuristics sensitive to device model structure, matrix sparsity, and anticipated conflict density.
• Solver-level co-optimization to exploit simulation-intrinsic sparsity patterns and dynamic partitioning.
• Deployment within closed-loop AI/LLM-based design agents, evaluating end-to-end scalability and impact on design cycle time.

Conclusion

EEspice delivers a modular, open-source circuit simulation platform that leverages graph coloring-based parallel device model evaluation to eliminate stamping bottlenecks characteristic of conventional SPICE-like engines. Demonstrating up to $45\times$ speedup on many-core CPUs with accuracy parity to established simulators, EEspice enables a new class of high-throughput, optimization-in-the-loop EDA workflows. Realizing the next order-of-magnitude gains will require parallel solver advancements, which, when coupled with coloring-based device partitioning, provide a promising path toward scalable simulation infrastructure for data-driven and AI-powered IC design automation.