- The paper develops a self-calibrating SDR that uses a length-matched PCB loopback network to estimate per-channel timing, phase, and frequency-selective gain errors without external test equipment.
- A two-stage fractional-delay/phase compensator and regularized FIR equalizer improve simulated nulling from 7.63 dB to −35.08 dB, outperforming a single-stage FIR that reaches −11.49 dB.
- Hardware experiments on a seven-element RFSoC array improve average null depth from −13.12 dB to −45.85 dB while sharply reducing variation across subcarriers, supporting practical deep-null formation.
Motivation and problem statement
Null forming—steering an array so that its response vanishes in a chosen direction—is substantially more sensitive to hardware imperfections than conventional beam steering. Because nulls are intrinsically narrow, small per-channel mismatches in timing, phase, or gain can destroy suppression: prior measurements show noticeable degradation once calibration errors exceed roughly 5∘, and measured null depths of about 30 dB under amplitude and phase deviations within ±0.5 dB and ±5∘ (2604.02498). This sensitivity is acute for software-defined radios (SDRs), whose RF chains exhibit non-identical, frequency-selective responses due to manufacturing tolerances, unequal routing lengths, and temperature drift. Conventional calibration remedies—VNA-assisted two-step procedures or over-the-air references with separate local oscillators—require costly instrumentation and suffer from phase-synchronization errors.
The paper addresses this by developing a self-calibrating SDR that estimates and compensates its own per-channel offsets via a loopback structure, targeting fully digital beam- and null-forming over 3.0–3.5 GHz, a band of particular interest to Department of Defense spectrum-sharing initiatives.
Self-calibration architecture
The key hardware idea is a calibration board in which a single reference transmitter feeds a known pilot through a Wilkinson divider, directionally coupled into every receiver antenna feed. The transmission lines from the reference to each coupler are length-matched on the PCB, so the calibration-path responses hm′[n] are nearly identical across channels (hm′[n]≈h′[n]). Under this approximation, any channel-dependent variation observed during self-calibration is attributable to the RF chain responses {hm[n]} themselves—an assumption enabled by fabricating the distribution network directly on the PCB rather than using commercial off-the-shelf combiners and couplers, which introduce non-negligible imbalance. The design reduces mismatch to lithographic tolerances at low cost.
The platform comprises a Xilinx RFSoC ZCU111 (eight 14-bit DACs, eight 12-bit ADCs), a front-end MIMO transceiver board, and the self-calibration antenna front end. It supports both standalone SDR operation and use as a beamforming/frequency-conversion add-on for existing base stations. Transmit-array calibration is symmetric but must be performed element by element, since a single reference receive antenna cannot separate simultaneous transmissions without degrading the calibration SINR; compensation is applied pre-transmission rather than in post-processing.
Calibration algorithm
The procedure models each channel's frequency response as
Hm[k]=Gm[k]e−jN2πkτmejϕm,
with per-channel timing offset τm, phase offset ϕm, and frequency-selective gain Gm[k]. Compensation is split into two cascaded FIR stages, ±0.50: a fractional-delay/phase compensator ±0.51 (windowed, odd length ±0.52) followed by a regularized least-squares gain equalizer ±0.53 of length ±0.54 with closed-form solution. The paper argues explicitly that a single-stage FIR attempting to learn phase distortion and residual gain mismatch jointly is inefficient with limited taps—a claim borne out numerically below.
Timing estimation applies a grid of fractional shift hypotheses ±0.55, correlates against the known QPSK pilot, and selects the hypothesis maximizing the matched-filter peak; because ±0.56 is strictly real and positive, the peak location identifies ±0.57 and the peak's angle yields ±0.58. The method relies on the noise being negligible at the matched-filter peak, so accuracy degrades with noise power—a dependence quantified in simulation.
Simulation results
With ±0.59, ±5∘0, ±5∘1, ±5∘2, ±5∘3, steering toward ±5∘4 and nulling ±5∘5, the average nulling ratio improves from 7.63 dB before calibration to −35.08 dB after calibration. A one-stage FIR filter of length ±5∘6 achieves only −11.49 dB, confirming the two-stage decomposition. Noise sweeps show the post-calibration standard deviation of the nulling ratio across frequency bins drops by about 40 dB at ±5∘7 relative to the uncalibrated case, indicating effective compensation of frequency selectivity; performance degrades monotonically as noise power increases, underscoring the importance of low-noise hardware.
Experimental validation
Experiments used a 7-element transmit array sending random QPSK symbols over 200 active subcarriers out of 1024 bins, with no strong reflectors within 5 m of the SDR. To isolate the accuracy of the offset estimates, compensation was applied directly in the frequency domain rather than via time-domain FIR filtering. Results:
| Metric |
Pre-calibration |
Post-calibration |
| Average nulling ratio |
−13.12 dB |
−45.85 dB |
| Std. dev. across subcarriers |
−13.89 dB |
−50.33 dB |
The roughly 33 dB improvement in average null depth, together with the near-elimination of inter-subcarrier variability, validates the offset-estimation algorithm on practical hardware. Notably, the experimental nulling ratio (−45.85 dB) exceeds the simulated value (−35.08 dB), though the two are not directly comparable given different array sizes, active bandwidths, and compensation domains.
Limitations and open questions
Several caveats bear on these results. First, the central claim rests on the PCB-level approximation ±5∘8; the paper asserts this holds "in practice" but does not quantify residual calibration-path mismatch or its contribution to the achieved null depths. Second, the experimental validation compensates offsets in the frequency domain, leaving the end-to-end performance of the actual FIR filters on measured data unverified. Third, the matched-filter-based phase estimate assumes negligible noise at the peak, and the simulation shows graceful but nonzero degradation with noise power; robustness under realistic interference conditions is not characterized. Fourth, calibration runs execute on the host computer rather than on-chip—the authors note that accelerating the pipeline on the FPGA remains future work—and temperature-dependent drift implies recalibration cadence requirements that the paper does not address. Finally, transmit-side calibration was described but not experimentally reported.
Conclusion
The paper presents a physically structured self-calibration approach for fully digital arrays: a directionally coupled, length-matched PCB calibration network isolates RF-chain impairments, and a lightweight two-stage FIR procedure compensates per-channel timing, phase, and gain-curve offsets. Validated on an open-source RFSoC platform in the 3.0–3.5 GHz band, the method lifts average nulling ratios from −13.12 dB to −45.85 dB experimentally, demonstrating that deep null formation is attainable on commodity SDR hardware without external laboratory equipment.