- The paper demonstrates a fully coupled, non-homogenized EM-thermal-mechanical workflow that simulates a 26-layer package with 21.1 million EM degrees of freedom in about 80 seconds on one NVIDIA A100.
- The framework synchronizes electromagnetic and thermal updates every 20 femtoseconds, capturing localized adiabatic temperature spikes from 40 GHz data bursts that static power maps can miss.
- The results show sub-bump von Mises stress concentrations at copper–underfill interfaces, offering earlier reliability guidance while remaining limited by adiabatic boundaries, quasi-static mechanics, and idealized material models.
Overview
The paper presents a GPU-accelerated transient co-simulation framework that couples electromagnetic, thermal, and mechanical solvers for full-scale, non-homogenized analysis of advanced packages. Its stated objective is to eliminate the fidelity-versus-speed trade-off that dominates early-stage (pathfinding) package design, in which practitioners conventionally rely on static power maps and homogenized material blocks. The authors argue that such approximations mask failure mechanisms driven by transient signal bursts—specifically adiabatic heating events and sub-bump-scale stress concentrations—and demonstrate their solver on a package adapted from the NEC SX-Aurora TSUBASA architecture, achieving total runtimes on the order of minutes on a single NVIDIA A100.
The electromagnetic stage uses a matrix-free time-domain method on a non-uniform grid, discretizing Maxwell's equations into a second-order ODE in the electric field with diagonal mass and damping matrices. An explicit central-difference update, subject to the CFL condition, reduces each step to sparse matrix-vector products (SpMVs), which map naturally onto GPUs. Conductivity is temperature-dependent via the standard linearized form σ(T)=σ0​/(1+α(T−T0​)), providing the EM-to-thermal coupling.
The thermal solver runs on the same finite-difference grid, eliminating interpolation errors at the coupling interface. Joule heating, Ptotal​=Dσ​e2, serves as the source term, advanced with Forward Euler. Notably, rather than exploiting the usual scale separation between EM and thermal time constants via subcycling or averaged power, the authors strictly synchronize both solvers at the EM time step. This choice is justified by their target regime: fast signal spikes producing nearly instantaneous, localized adiabatic temperature rises. This is a deliberate design decision that trades efficiency for the ability to capture transient thermal shock, and it implicitly assumes that such adiabatic events—not slower diffusive heating cycles—are the dominant early-stage reliability concern.
The mechanical stage applies linear thermoelasticity with HEX8 finite elements and 2×2×2 Gauss quadrature, driven solely by the transient thermal strain field (no external body forces). Von Mises stress is evaluated per element as the yield/failure indicator. The mechanical system is solved quasi-statically at peak-temperature snapshots rather than time-marched dynamically, an assumption that is reasonable for the sub-ns window considered but leaves inertial (stress-wave) effects unmodeled.
Test structure and excitation
The simulated package spans 60×60 mm² with a 2.80 mm stack of 26 layers: organic substrate, silicon interposer, and logic/HBM tiers, with micro-bump arrays and differential routing explicitly resolved—all material interfaces retain distinct isotropic elastic properties (e.g., copper E=128 GPa, α=17 ppm; solder E=50 GPa, α=25 ppm). Boundary conditions comprise PMC truncation for EM, adiabatic thermal boundaries (defensible only within the very short transient window), and a three-node kinematic mount for mechanics that suppresses rigid-body motion without inducing artificial constraint stress.
The excitation superimposes three temporally distinct waveforms: a 20–60 ps Ricker-wavelet "Trigger" on the substrate, a 5 GHz "Logic Noise" sine over 0–300 ps, and a 40 GHz carrier with a 3-bit Gaussian pulse-train "Data Burst" (80–230 ps) on the HBM stacks. Deterministic jitter (up to ±20% amplitude, ±10% width, ±10 ps phase) is applied per port to generate realistic common-mode noise. This is a more physically grounded excitation than the idealized static power maps the paper criticizes, though it remains synthetic rather than measured workload data.
The implementation combines C++, cuSPARSE, and custom CUDA kernels for the explicit EM-thermal march, with AmgX-based FGMRES preconditioned by algebraic multigrid for the mechanical solves on an A100 80GB. The mesh of 376×408×45 cells yields roughly 21.1M EM DOFs, 7.1M thermal DOFs, and 21.3M mechanical DOFs. Over a 300 ps window at Δt=20 fs (15,000 steps), the coupled march completes in approximately 79.71 seconds, with each static mechanical solve at a peak-temperature snapshot taking about 62 seconds. These runtimes—minutes in total for a full-scale, explicitly resolved package—are the paper's central quantitative claim, and they support the feasibility of multiphysics-informed design iteration at pathfinding stage.
Results and reliability findings
At the substrate-interposer C4 bump interface (Ptotal​=Dσ​e20 mm), the transient Joule power maps show heat injection migrating spatially between substrate vias, logic, and HBM bumps over the 300 ps window. The terminal temperature field exhibits sharp adiabatic spikes localized at signal traces and micro-bumps, in contrast to the smooth gradients steady-state analysis would produce. The authors' strong claim here is that significant thermal gradients develop before diffusion equilibrates the structure, constituting a thermal shock regime distinct from the slow cycling conventionally modeled in package reliability.
The mechanical response computed from the peak temperature profile shows non-uniform planar displacement at the interface, generating shear and out-of-plane loading, with Von Mises stress concentrating at CTE-mismatched material boundaries (copper bumps versus underfill/dielectric) at sub-bump scale. The paper asserts these concentrations are "completely averaged out" by homogenization, implying that homogenized early-stage flows would miss the corresponding delamination risk indicators entirely. If borne out across designs, this means sign-off-level reliability hazards could be surfaced during pathfinding rather than at final verification, where remediation is costly.
Limitations and open questions
Several assumptions bound the results. The thermal boundaries are adiabatic, valid only for the sub-nanosecond window; extending the observation horizon would require convective or sink boundary models. The mechanical solve is quasi-static at temperature snapshots, omitting dynamic stress-wave response to the picosecond-scale thermal shock the solver itself resolves. Material models are linear elastic and isotropic with perfectly bonded interfaces—no slip, delamination, or plasticity—so absolute stress magnitudes near yield should be interpreted cautiously. The excitation is synthetic with deterministic jitter rather than measured workload currents. The paper also reports results at a single representative interface plane and a single design point; the generality of the adiabatic-stress findings across stack-ups, power profiles, and longer time windows remains an open question, as does the correlation of the predicted sub-bump stress concentrations against measured failure data.
Conclusion
The paper demonstrates that explicit, non-homogenized transient EM-thermal-mechanical co-simulation of a full-scale advanced package is computationally tractable on a single GPU, with total runtimes of minutes. The key technical contributions are the strictly synchronized explicit EM-thermal coupling at the EM time step and the GPU-resident solution chain from Maxwell's equations through Joule heating to thermoelastic Von Mises stress. The demonstrated capability to expose signal-induced adiabatic temperature spikes and sub-bump-scale CTE-mismatch stress concentrations—phenomena the authors argue are invisible to steady-state and homogenized baselines—offers a concrete path to embedding sign-off-level physics in early-stage package design, contingent on the assumptions of adiabatic boundaries, quasi-static mechanics, and linear elastic materials being appropriate to the failure modes of interest.