Eight-Qubit Operation of a 300 mm SiMOS Foundry-Fabricated Device

Abstract: Silicon spin qubits are a promising candidate for quantum computing, thanks to their high coherence, high controllability and manufacturability. However, the most scalable complementary metal-oxide-semiconductor (CMOS) based implementations have so far been limited to a few qubits. Here, to take a step towards large scale systems, we tune and coherently control an eight-dot linear array of silicon spin qubits fabricated in 300 mm CMOS-compatible foundry process, establishing operational scalability beyond the two-qubit regime. All eight qubits are successfully tuned and characterized as four double dot pairs, exhibiting Ramsey dephasing times $T_2^*$ up to 41(2) $μ$s and Hahn-echo coherence times $T_2^{\mathrm{Hahn}}$ up to 1.31(4) ms. Readout of the central four qubits is achieved via a cascaded charge-sensing protocol, enabling simultaneous high-fidelity measurements of the entire multi-qubit array. Additionally, we demonstrate a two-qubit gate operation between adjacent qubits with low phase noise. We demonstrate here that we can scale silicon spin qubit arrays to medium-sized arrays of 8 qubits while maintaining coherence of the system.

• The paper demonstrates the scalable integration of eight silicon spin qubits in a 300 mm CMOS foundry process that meets benchmarks for fault-tolerant quantum computing.
• The paper utilizes polycrystalline silicon gates and cascaded charge-sensing to achieve coherent control, with Rabi frequencies of 141–204.5 kHz and dephasing times up to 41 µs.
• The paper validates two-qubit CZ gates via exchange interaction with low charge noise, paving the way for error-corrected quantum architectures.

Eight-Qubit Operation of a 300 mm SiMOS Foundry-Fabricated Device

Introduction

This study presents the coherent operation and characterization of an eight-qubit linear array of silicon spin qubits implemented in a 300 mm complementary metal-oxide-semiconductor (CMOS)-compatible metal–oxide–semiconductor (MOS) foundry process. The primary innovation involves scaling device and control methods, previously demonstrated for one or two qubits, to an eight-dot system and validating the performance metrics required for fault-tolerant quantum computation using industry-standard fabrication processes.

Device Architecture and Operational Protocols

The device is structured as a four-double-quantum-dot (DQD) linear chain, each DQD comprising two qubits captured under adjacent plunger gates. Key features include polycrystalline silicon gates to minimize strain and charge noise, with SETs situated for charge and spin detection at both array terminations. The process ensures compatibility with large-scale integration and leverages high-purity $^{28}$Si to suppress nuclear spin noise.

Charge initialization and electron loading routines are implemented to independently configure the occupation of each dot, permitting robust control over the multi-qubit electron environment. Spin states are manipulated and measured using high-fidelity ESR, and entangling gates are realized via the Heisenberg exchange interaction, controlled by tuning the inter-dot potential barriers.

Of particular note, a cascaded charge-sensing architecture enables simultaneous high-fidelity readout of the central dots, crucial for scaling beyond edge-state measurements.

Coherent Control and Qubit Performance

Each quantum dot in the linear array is tuned to host a single electron and thus operate as an effective spin-1/2 system. Coherent single-qubit operations are executed by detuned ESR-based microwave control, achieving Rabi frequencies ranging from 141(1) kHz to 204.5(6) kHz. The gate design permits a narrow spread in $g$-factors ($\Delta g \approx 2.17 \times 10^{-3}$ across the array), facilitating individual and global qubit addressability under fixed field configurations.

Ramsey dephasing times ($T_2^*$) are reported up to 41(2) $\mu$s, which exceed or match previous reports in Si-MOS devices, demonstrating that coherence properties persist even with the increased device complexity inherent to larger arrays. Hahn-echo coherence times ($T_\text{Hahn}$) reach 1.31(4) ms, consistent with or near leading academic and foundry devices. These results validate that state-of-the-art coherence and control fidelities can be maintained in multi-qubit, foundry-fabricated systems.

Two-Qubit Gates and Charge Noise Robustness

The study demonstrates two-qubit CZ gates mediated by exchange interaction in one double-dot pair (P1–P2), with pulsed gate calibration and deterministic phase accumulation. The observed exchange turn-on follows an exponential dependence on the applied barrier gate voltage, with low phase noise and strong preservation of phase coherence, indicative of a low-charge noise environment.

Attempts to implement two-qubit gates in other pairs were limited by device geometry (barrier gate layout, dot size, electron wavefunction overlap). The experiments suggest increased electron occupation can enhance exchange coupling but introduce trade-offs in terms of reduced charging energy and increased tuning complexity.

Importantly, the robustness to charge noise—a foundational challenge for semiconductor qubits—is evidenced by the ability to reliably tune, address, and entangle spins in a foundry-fabricated platform. The system responds favorably to feedback-based correction protocols, underscoring the applicability of scalable error-correction and dynamical decoupling techniques in this architecture.

Implications for Scalable Quantum Computing

This work provides direct experimental evidence that operational scalability of silicon spin qubits is feasible utilizing industrial CMOS processes, extending beyond previously demonstrated single- and two-qubit devices. The eight-qubit array confirms the transferability of both device physics and control strategies for larger quantum dot networks. The implementation of a cascaded, simultaneous readout for internal qubits addresses one of the critical bottlenecks for scalable, multiplexed quantum information extraction.

From an architectural perspective, decomposing the linear chain into DQD cells mitigates the calibration overhead for large $N$, supporting modular approaches to scaling. The demonstrated performance metrics are sufficient for implementing initial error-correction codes, with immediate practical relevance for logical qubit experiments within linear arrays.

However, for large-scale, fault-tolerant quantum computers, further development of higher-connectivity qubit arrays (e.g., bilinear or 2D) and all-to-all control will be essential. The foundry platform provides a clear path to engineer such complex couplings, provided further innovation in gate density and interconnects. Future efforts must focus on reproducibility, on-demand control of exchange in all pairs, and integration with CMOS cryogenic control circuitry.

Conclusion

This research establishes a comprehensive proof-of-principle for medium-scale (eight-qubit) silicon spin qubit arrays fabricated in an advanced industrial foundry process, with strong coherence, high-fidelity individual and two-qubit gates, and scalable readout. The methodology, grounded in modular DQD cells and robust charge noise management, validates the translatability of foundry-fabricated Si-MOS devices to larger quantum processors.

By demonstrating these capabilities in a 300 mm CMOS environment, the work sets critical benchmarks for the quantum industry and strengthens the feasibility of silicon-based quantum information processors that leverage existing semiconductor infrastructure. This research thus points toward the imminent possibility of scalable quantum architectures and motivates future development in error-corrected, large-scale quantum computing with spin qubits.