SAFE-SiP: Secure Authentication Framework for System-in-Package Using Multi-party Computation

Abstract: The emergence of chiplet-based heterogeneous integration is transforming the semiconductor, AI, and high-performance computing industries by enabling modular designs and improved scalability. However, assembling chiplets from multiple vendors after fabrication introduces a complex supply chain that raises serious security concerns, including counterfeiting, overproduction, and unauthorized access. Current solutions often depend on dedicated security chiplets or changes to the timing flow, which assume a trusted SiP integrator. This assumption can expose chiplet signatures to other vendors and create new attack surfaces. This work addresses those vulnerabilities using Multi-party Computation (MPC), which enables zero-trust authentication without disclosing sensitive information to any party. We present SAFE-SiP, a scalable authentication framework that garbles chiplet signatures and uses MPC for verifying integrity, effectively blocking unauthorized access and adversarial inference. SAFE-SiP removes the need for a dedicated security chiplet and ensures secure authentication, even in untrusted integration scenarios. We evaluated SAFE-SiP on five RISC-V-based System-in-Package (SiP) designs. Experimental results show that SAFE-SiP incurs minimal power overhead, an average area overhead of only 3.05%, and maintains a computational complexity of 2^192, offering a highly efficient and scalable security solution.

An Essay on SAFE-SiP: Secure Authentication Framework for System-in-Package Using Multi-party Computation

The paper under review introduces SAFE-SiP, an authentication framework designed for System-in-Package (SiP) environments that utilize heterogeneous integration of chiplets sourced from diverse vendors. These environments, while enhancing modular design and scalability, present significant security challenges due to the complex supply chain. In addressing these challenges, SAFE-SiP proposes a novel solution leveraging Multi-party Computation (MPC) to provide secure, zero-trust authentication of chiplet components without exposing sensitive vendor-provided signature information.

SAFE-SiP builds on the foundational cryptographic technique of garbling circuits. Garbling circuits are employed to transform chiplet signatures into encrypted forms that ensure confidentiality during both inter-chiplet communication and supply chain interactions. This is achieved without necessitating a dedicated security chiplet, which traditional approaches often require. By integrating the garbling circuit directly into the existing chiplet functionality, the potential attack surfaces—such as counterfeiting, unauthorized access, or Trojan insertion—are minimized and made more complex for adversarial exploitation.

The paper provides extensive numerical results highlighting the efficacy of SAFE-SiP. Experimental evaluations across five RISC-V-based benchmarks demonstrate the framework's efficient integration, with minimal area overhead of only 3.05% and a computational complexity sustaining at $2^{192}$ security levels. Remarkably, the power overhead remains low, maintaining scalability across different chiplet configurations. These results underscore the practical applicability of SAFE-SiP in real-world scenarios, proving its capability as a cost-efficient security solution that doesn't significantly burden existing system performance metrics.

Security analysis within the paper reveals SAFE-SiP's robustness against a variety of attack vectors typical in SiP environments. The framework effectively counters removal, replay, tampering, denial-of-service, and forging attacks through its layered cryptographic protections. Particularly, the garbling and SHA-256 core utilization enhance resistance to tampering and spoofing by making extracted authentication data incredibly difficult to reverse-engineer. Furthermore, SAFE-SiP ensures the integrity of data communication across chiplets in untrusted environments while adhering to standards like IEEE 1500, providing not only resistance but also verification against unauthorized circuit modifications.

In terms of implications, the development and deployment of SAFE-SiP stand to benefit semiconductor industries significantly. Its introduction mitigates critical security issues inherent in multi-vendor and post-fabrication scenarios, crucial for reliable SiP integration. Moreover, by securing chiplet assemblies with minimal overhead, SAFE-SiP retains the flow of high-performance computing systems, maintaining both economic feasibility and scalability. These advancements could influence future SiP designs, promoting broader adoption of zero-trust models throughout supply chains and fostering innovation in secure modular architectures.

Overall, SAFE-SiP emerges as a robust solution for enhancing the security framework within heterogeneous integration environments, aligning modular efficiency and cryptographic resilience. Its ability to ensure authentication integrity under adversarial conditions makes the framework essential for future SiP assembly security paradigms, aiming for long-term reliable component verification.