TAXI: Traveling Salesman Problem Accelerator with X-bar-based Ising Macros Powered by SOT-MRAMs and Hierarchical Clustering

Abstract: Ising solvers with hierarchical clustering have shown promise for large-scale Traveling Salesman Problems (TSPs), in terms of latency and energy. However, most of these methods still face unacceptable quality degradation as the problem size increases beyond a certain extent. Additionally, their hardware-agnostic adoptions limit their ability to fully exploit available hardware resources. In this work, we introduce TAXI -- an in-memory computing-based TSP accelerator with crossbar(Xbar)-based Ising macros. Each macro independently solves a TSP sub-problem, obtained by hierarchical clustering, without the need for any off-macro data movement, leading to massive parallelism. Within the macro, Spin-Orbit-Torque (SOT) devices serve as compact energy-efficient random number generators enabling rapid "natural annealing". By leveraging hardware-algorithm co-design, TAXI offers improvements in solution quality, speed, and energy-efficiency on TSPs up to 85,900 cities (the largest TSPLIB instance). TAXI produces solutions that are only 22% and 20% longer than the Concorde solver's exact solution on 33,810 and 85,900 city TSPs, respectively. TAXI outperforms a current state-of-the-art clustering-based Ising solver, being 8x faster on average across 20 benchmark problems from TSPLib.

• The paper introduces TAXI, a co-designed hardware accelerator that decomposes large TSPs via hierarchical clustering for parallel in-macro optimization.
• It employs an X-bar-based Ising macro with SOT-MRAM-driven stochastic annealing, reducing energy and enhancing solution quality through efficient MAC operations.
• TAXI achieves near-optimal solutions—only 22% longer than Concorde for 33,810 cities—and operates 8x faster than previous state-of-the-art Ising solvers.

This paper introduces TAXI, a specialized hardware accelerator designed to solve large-scale Traveling Salesman Problems (TSPs) using an Ising model approach implemented with in-memory computing (IMC). The core problem addressed is the inefficiency of traditional TSP solvers (exponential time complexity) and existing Ising-based hardware accelerators (quality degradation, memory bottlenecks, slow/bulky random number generators) when dealing with very large problem instances (up to 85,900 cities).

TAXI employs a hardware-algorithm co-design strategy. The key components and implementation details are:

1. Hierarchical Clustering Algorithm:
   • Large TSPs are decomposed into smaller, manageable sub-problems using bottom-up agglomerative hierarchical clustering with Ward linkage. This method is chosen for its robustness to outliers compared to K-means.
   • The clustering proceeds until the number of centroids at the highest level is small enough to be handled by a single Ising macro.
   • The solving process is top-down. After solving the top-level TSP, the inter-cluster routes for the next level down are fixed by identifying the closest city pairs between adjacent clusters in the determined sequence.
   • This fixing of inter-cluster routes allows sub-problems (intra-cluster routes) to be solved independently and in parallel by dedicated hardware units, minimizing dependencies and enhancing parallelism.
2. X-bar-based Ising Macro:
   • Each sub-problem is mapped onto a dedicated hardware unit called an Ising macro, based on a crossbar (Xbar) array architecture.
   • Energy Minimization: The macro uses Multiplication-and-Accumulation (MAC) operations within the Xbar array to calculate the energy ($H_i$) or, in this TSP mapping, the relative distance ($D_{x,i}$) for visiting city $x$ at step $i$.
     • Inter-city distances ($D_{A-B}$) are converted into conductance values ($W_D(A,B)$) and programmed into the Xbar cells (Eq. 4). Bit precision ($B_{Precision}$) can be adjusted (e.g., 2, 3, or 4-bit).
     • The Xbar array is partitioned: $B$ partitions store the distance matrix ($W_D$), and one partition (Spin Storage - SS) stores the current solution (visiting order, $\sigma_{k,i}$) using SOT-MRAM cells (LRS for visited, HRS for not visited).
     • To calculate the distance for visiting city $x$ at order $i$, the visiting information from orders $i-1$ and $i+1$ is read from the SS partition and used as input voltages to the rows of the $W_D$ partitions. The resulting column currents represent the distances ($D_{x,i}$ based on Eq. 5). This superposition reduces Xbar size.
   • Stochasticity & Annealing:
     • Spin-Orbit-Torque Magnetic Random Access Memory (SOT-MRAM) devices are used peripherally to the Xbar as compact, energy-efficient random number generators (RNGs).
     • SOT-MRAMs exhibit stochastic switching behavior within a specific current range ($I_{stoch}$) (Fig. 4c inset). TAXI leverages this by applying a controlled current to $N$ SOT devices (where $N$ is the sub-problem size) to generate a stochastic binary vector.
     • This vector masks the calculated distances ($D_{x,i}$), allowing the system to potentially escape local minima by considering only a random subset of possible next cities.
     • "Natural annealing" is achieved by gradually reducing the write current ($I_{write}$) applied to the stochastic SOT-MRAM units over iterations. TAXI uses the sigmoidal $P_{sw}$ vs $I_{write}$ curve of SOT-MRAM, starting at 20% probability and linearly decreasing the current until 1% probability is reached, enabling faster initial optimization and finer convergence later.
   • Decision Making & Update:
     • The (potentially masked) currents representing distances flow through current mirrors and then into an ArgMax circuit (Fig. 4d), which selects the column (city) corresponding to the largest current (shortest effective distance).
     • The ArgMax output (a one-hot vector) is directly used to update the corresponding column in the Spin Storage (SS) partition of the Xbar, programming the selected city's SOT-MRAM to LRS and others to HRS for that visiting order.
3. Parallel Architecture & In-Macro Computing:
   • TAXI maps the hierarchical clustering algorithm onto a spatial IMC architecture (simulated using a modified PUMA framework).
   • Multiple Ising macros operate in parallel, each solving a TSP sub-problem entirely within its local Xbar array and peripheral circuits ("in-macro"). This minimizes data movement to/from off-chip memory during the core optimization process, significantly reducing latency and energy compared to prior IMC approaches that stored spin states externally.

Evaluation and Results:

• Simulations: The system was evaluated using C++ simulations (algorithmic performance, considering non-idealities), Cadence Spectre (circuit-level performance of a 12-city macro in 65nm TSMC), and a modified PUMA architecture simulator (system-level latency/energy for large TSPs, scaled to 65nm).
• Solution Quality: TAXI achieves near-optimal solutions, only 22% and 20% longer than the exact Concorde solver for 33,810 and 85,900 city TSPs, respectively. It outperforms prior state-of-the-art clustering-based Ising solvers like Neuro-Ising [neuro-ising] and CIMA [TSP-shimeng2] on large benchmarks (Fig. 5c). Lower bit precision (e.g., 2-bit) maintains quality within ~2% of 4-bit while improving energy efficiency (Fig. 5b). Smaller cluster sizes generally yield better solutions (Fig. 5a).
• Performance:
  • Circuit simulations show a single iteration (superposition, optimization, update) takes ~9ns for a 12-city macro, consuming ~46 pJ (4-bit) (Table I).
  • Architecture simulations show TAXI is 8x faster on average than Neuro-Ising across 20 TSPLib benchmarks.
  • For the largest TSP (85,900 cities), TAXI takes ~375s, dominated by clustering/fixing time (Fig. 6b), compared to a projected 136 years for the exact solver.
  • Energy efficiency is significantly better than prior Ising solvers (Table II), although data transfer energy becomes dominant for large problems when included.

In summary, TAXI presents a hardware accelerator for large TSPs combining hierarchical clustering with parallel, in-macro Ising computation using SOT-MRAM-enhanced Xbar arrays. The co-design approach leverages the unique properties of SOT-MRAM for efficient stochastic annealing and minimizes data movement, leading to significant improvements in speed, energy efficiency, and solution quality for problems up to the largest TSPLIB instance.