Papers
Topics
Authors
Recent
Search
2000 character limit reached

Energy Efficient Dual Designs of FeFET-Based Analog In-Memory Computing with Inherent Shift-Add Capability

Published 25 Oct 2024 in cs.ET | (2410.19593v1)

Abstract: In-memory computing (IMC) architecture emerges as a promising paradigm, improving the energy efficiency of multiply-and-accumulate (MAC) operations within DNNs by integrating the parallel computations within the memory arrays. Various high-precision analog IMC array designs have been developed based on both SRAM and emerging non-volatile memories. These designs perform MAC operations of partial input and weight, with the corresponding partial products then fed into shift-add circuitry to produce the final MAC results. However, existing works often present intricate shift-add process for weight. The traditional digital shift-add process is limited in throughput due to time-multiplexing of ADCs, and advancing the shift-add process to the analog domain necessitates customized circuit implementations, resulting in compromises in energy and area efficiency. Furthermore, the joint optimization of the partial MAC operations and the weight shift-add process is rarely explored. In this paper, we propose novel, energy efficient dual designs of FeFET based high precision analog IMC featuring inherent shift-add capability. We introduce a FeFET based IMC paradigm that performs partial MAC in each column, and inherently integrates the shift-add process for 4-bit weights by leveraging FeFET's analog storage characteristics. This paradigm supports both 2's complement mode and non-2's complement mode MAC, thereby offering flexible support for 4-/8-bit weight data in 2's complement format. Building upon this paradigm, we propose novel FeFET based dual designs, CurFe for the current mode and ChgFe for the charge mode, to accommodate the high precision analog domain IMC architecture.Evaluation results at circuit and system levels indicate that the circuit/system-level energy efficiency of the proposed FeFET-based analog IMC is 1.56$\times$/1.37$\times$ higher when compared to SOTA analog IMC designs.

Definition Search Book Streamline Icon: https://streamlinehq.com
References (36)
  1. Y. LeCun et al., “Deep learning,” Nature, vol. 521, no. 7553, pp. 436–444, 2015.
  2. Z. Yan et al., “Computing-in-memory neural network accelerators for safety-critical systems: Can small device variations be disastrous?,” in IEEE/ACM ICCAD, pp. 1–9, 2022.
  3. N. Verma et al., “In-memory computing: Advances and prospects,” IEEE Solid-State Circuits Magazine, vol. 11, no. 3, pp. 43–55, 2019.
  4. Z. Yan et al., “Swim: Selective write-verify for computing-in-memory neural accelerators,” in ACM/IEEE DAC, pp. 277–282, 2022.
  5. A. Biswas et al., “Conv-ram: An energy-efficient sram with embedded convolution computation for low-power cnn-based machine learning applications,” in 2018 IEEE ISSCC, pp. 488–490, 2018.
  6. X. Si et al., “24.5 a twin-8t sram computation-in-memory macro for multiple-bit cnn-based machine learning,” in 2019 IEEE ISSCC, pp. 396–398, 2019.
  7. Q. Dong et al., “15.3 a 351tops/w and 372.4 gops compute-in-memory sram macro in 7nm finfet cmos for machine-learning applications,” in 2020 IEEE ISSCC, pp. 242–244, 2020.
  8. X. Si et al., “15.5 a 28nm 64kb 6t sram computing-in-memory macro with 8b mac operation for ai edge chips,” in 2020 IEEE ISSCC, pp. 246–248, 2020.
  9. J. Yue et al., “14.3 a 65nm computing-in-memory-based cnn processor with 2.9-to-35.8 tops/w system energy efficiency using dynamic-sparsity performance-scaling architecture and energy-efficient inter/intra-macro data reuse,” in 2020 IEEE ISSCC, pp. 234–236, 2020.
  10. J.-W. Su et al., “16.3 a 28nm 384kb 6t-sram computation-in-memory macro with 8b precision for ai edge chips,” in 2021 IEEE ISSCC, vol. 64, pp. 250–252, 2021.
  11. C. Zhuo et al., “Design of ultra-compact content addressable memory exploiting 1t-1mtj cell,” IEEE TCAD, 2022.
  12. Q. Huang et al., “Fefet based in-memory hyperdimensional encoding design,” IEEE TCAD, 2023.
  13. A. Sebastian et al., “Memory devices and applications for in-memory computing,” Nature Nanotechnology, vol. 15, no. 7, pp. 529–544, 2020.
  14. C.-X. Xue et al., “16.1 a 22nm 4mb 8b-precision reram computing-in-memory macro with 11.91 to 195.7 tops/w for tiny ai edge devices,” in 2021 IEEE ISSCC, pp. 245–247, 2021.
  15. J.-M. Hung et al., “A four-megabit compute-in-memory macro with eight-bit precision based on cmos and resistive random-access memory for ai edge devices,” Nature Electronics, vol. 4, no. 12, pp. 921–930, 2021.
  16. J.-M. Hung et al., “8-b precision 8-mb reram compute-in-memory macro using direct-current-free time-domain readout scheme for ai edge devices,” IEEE JSSC, vol. 58, no. 1, pp. 303–315, 2022.
  17. T. Soliman et al., “Ultra-low power flexible precision fefet based analog in-memory computing,” in 2020 IEEE IEDM, pp. 29–2, 2020.
  18. X. Yin et al., “Ferroelectric ternary content addressable memories for energy-efficient associative search,” IEEE TCAD, vol. 42, no. 4, pp. 1099–1112, 2022.
  19. D. Saito et al., “Analog in-memory computing in fefet-based 1t1r array for edge ai applications,” in 2021 IEEE Symposium on VLSI Technology, pp. 1–2, 2021.
  20. Q. Huang et al., “Computing-in-memory using ferroelectrics: From single-to multi-input logic,” IEEE Design & Test, vol. 39, no. 2, pp. 56–64, 2021.
  21. X. Yin et al., “Ferroelectric compute-in-memory annealer for combinatorial optimization problems,” Nature Communications, vol. 15, no. 1, p. 2419, 2024.
  22. L. Liu et al., “A reconfigurable fefet content addressable memory for multi-state hamming distance,” IEEE Transactions on Circuits and Systems I: Regular Papers, 2023.
  23. H. Xu et al., “On the challenges and design mitigations of single transistor ferroelectric content addressable memory,” IEEE Electron Device Letters, 2023.
  24. C. Li et al., “A scalable design of multi-bit ferroelectric content addressable memory for data-centric computing,” in 2020 IEEE IEDM, pp. 29–3, 2020.
  25. T. Soliman et al., “First demonstration of in-memory computing crossbar using multi-level cell fefet,” Nature Electronics, vol. 14, no. 1, p. 6348, 2023.
  26. X. S. Hu et al., “In-memory computing with associative memories: A cross-layer perspective,” in 2021 IEEE IEDM, pp. 25–2, 2021.
  27. X. Yin et al., “Fecam: A universal compact digital and analog content addressable memory using ferroelectric,” IEEE Transactions on Electron Devices, vol. 67, no. 7, pp. 2785–2792, 2020.
  28. S. Shou et al., “See-mcam: Scalable multi-bit fefet content addressable memories for energy efficient associative search,” in 2023 IEEE/ACM ICCAD, pp. 1–9, 2023.
  29. X. Yin et al., “An ultracompact single-ferroelectric field-effect transistor binary and multibit associative search engine,” Advanced Intelligent Systems, vol. 5, no. 7, p. 2200428, 2023.
  30. H. Jiang et al., “Analog-to-digital converter design exploration for compute-in-memory accelerators,” IEEE Design & Test, vol. 39, no. 2, pp. 48–55, 2021.
  31. J. Hur et al., “Nonvolatile capacitive crossbar array for in-memory computing,” Advanced Intelligent Systems, vol. 4, no. 8, p. 2100258, 2022.
  32. D. Kleimaier et al., “Demonstration of a p-type ferroelectric fet with immediate read-after-write capability,” IEEE Electron Device Letters, vol. 42, no. 12, pp. 1774–1777, 2021.
  33. S. Thomann et al., “All-in-memory brain-inspired computing using fefet synapses,” Frontiers in Electronics, vol. 3, p. 833260, 2022.
  34. K. Ni et al., “A circuit compatible accurate compact model for ferroelectric-fets,” in 2018 IEEE symposium on VLSI technology, pp. 131–132, 2018.
  35. D. Reis et al., “Design and analysis of an ultra-dense, low-leakage, and fast fefet-based random access memory array,” IEEE JxCDC, vol. 5, no. 2, pp. 103–112, 2019.
  36. X. Peng et al., “Dnn+ neurosim: An end-to-end benchmarking framework for compute-in-memory accelerators with versatile device technologies,” in 2019 IEEE IEDM, pp. 32–5, 2019.
Citations (1)
View on Semantic Scholar

Summary

No one has generated a summary of this paper yet.

Sign Up to Summarize

Paper to Video (Beta)

No one has generated a video about this paper yet.

Sign Up to Generate All Videos Subscribe on YouTube

Whiteboard

No one has generated a whiteboard explanation for this paper yet.

Sign Up to Generate

Open Problems

We haven't generated a list of open problems mentioned in this paper yet.

Generate Now

Continue Learning

We haven't generated follow-up questions for this paper yet.

Generate Now

Collections

Sign up for free to add this paper to one or more collections.

Sign Up