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Hiding Information for Secure and Covert Data Storage in Commercial ReRAM Chips

Published 9 Jan 2024 in cs.ET and cs.CR | (2401.04411v1)

Abstract: This article introduces a novel, low-cost technique for hiding data in commercially available resistive-RAM (ReRAM) chips. The data is kept hidden in ReRAM cells by manipulating its analog physical properties through switching ($\textit{set/reset}$) operations. This hidden data, later, is retrieved by sensing the changes in cells' physical properties (i.e., $\textit{set/reset}$ time of the memory cells). The proposed system-level hiding technique does not affect the normal memory operations and does not require any hardware modifications. Furthermore, the proposed hiding approach is robust against temperature variations and the aging of the devices through normal read/write operation. The silicon results show that our proposed data hiding technique is acceptably fast with ${\sim}0.4bit/min$ of encoding and ${\sim}15.625bits/s$ of retrieval rates, and the hidden message is unrecoverable without the knowledge of the secret key, which is used to enhance the security of hidden information.

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References (29)
  1. M. Rostami, F. Koushanfar, J. Rajendran, and R. Karri, “Hardware security: Threat models and metrics,” in 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2013, pp. 819–823.
  2. S. Rai, S. Patnaik, A. Rupani, J. Knechtel, O. Sinanoglu, and A. Kumar, “Security promises and vulnerabilities in emerging reconfigurable nanotechnology-based circuits,” IEEE Transactions on Emerging Topics in Computing, vol. 10, no. 2, pp. 763–778, 2022.
  3. J. Rajendran, R. Karri, J. B. Wendt, M. Potkonjak, N. McDonald, G. S. Rose, and B. Wysocki, “Nano meets security: Exploring nanoelectronic devices for security applications,” Proceedings of the IEEE, vol. 103, no. 5, pp. 829–849, 2015.
  4. M. I. Rashid, F. Ferdaus, B. M. S. B. Talukder, P. Henny, A. N. Beal, and M. T. Rahman, “True random number generation using latency variations of fram,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 1, pp. 14–23, 2021.
  5. F. Ferdaus, B. M. S. Bahar Talukder, M. Sadi, and M. T. Rahman, “True random number generation using latency variations of commercial mram chips,” in 2021 22nd International Symposium on Quality Electronic Design (ISQED), 2021, pp. 510–515.
  6. “Crossbar reram technology,” https://www.crossbar-inc.com/technology/reram-advantages/, (Accessed: 8 May 2022).
  7. Fujitsu Semiconductor Memory Solution, “Reram (resistive random access memory),” 2019, (Accessed: 15 Oct 2021). [Online]. Available: https://www.fujitsu.com/jp/group/fsm/en/products/reram/
  8. F. Ferdaus, B. M. S. Bahar Talukder, and M. T. Rahman, “Watermarked reram: A technique to prevent counterfeit memory chips,” in Proceedings of the 2022 on Great Lakes Symposium on VLSI, ser. GLSVLSI ’22.   New York, NY, USA: Association for Computing Machinery, 2022.
  9. M. Arita, A. Takahashi, Y. Ohno, A. Nakane, A. Tsurumaki-Fukuchi, and Y. Takahashi, “Switching operation and degradation of resistive random access memory composed of tungsten oxide and copper investigated using in-situ tem,” in ICCD, vol. 5, 2015.
  10. M. Mao, Y. Cao, S. Yu, and C. Chakrabarti, “Optimizing latency, energy, and reliability of 1t1r ReRAM through appropriate voltage settings,” in ICCD, 2015, pp. 359–366.
  11. B. Govoreanu, S. Clima, I. P. Radu, Y.-Y. Chen, D. J. Wouters, and M. Jurczak, “Complementary role of field and temperature in triggering on/off switching mechanisms in Hf/HfO2HfsubscriptHfO2{\rm Hf}/{\rm HfO}_{2}roman_Hf / roman_HfO start_POSTSUBSCRIPT 2 end_POSTSUBSCRIPT resistive ram cells,” IEEE transactions on electron devices, vol. 60, no. 8, pp. 2471–2478, 2013.
  12. A. Cheddad, J. Condell, K. Curran, and P. Mc Kevitt, “Digital image steganography: Survey and analysis of current methods,” Signal Processing, vol. 90, no. 3, pp. 727–752, 2010.
  13. Y. Wang, W.-k. Yu, S. Q. Xu, E. Kan, and G. E. Suh, “Hiding information in flash memory,” in 2013 IEEE Symposium on Security and Privacy, 2013, pp. 271–285.
  14. F. Petitcolas, R. Anderson, and M. Kuhn, “Information hiding-a survey,” Proceedings of the IEEE, vol. 87, no. 7, pp. 1062–1078, 1999.
  15. N. Provos and P. Honeyman, “Hide and seek: an introduction to steganography,” IEEE Security Privacy, vol. 1, no. 3, pp. 32–44, 2003.
  16. Y. Pang et al., “A rram-based data hiding technique utilizing the impact of form condition on set performance,” in 2020 IEEE International Memory Workshop (IMW), 2020, pp. 1–4.
  17. I. Sutherland, G. Davies, and A. Blyth, “Malware and steganography in hard disk firmware,” Journal in computer virology, vol. 7, no. 3, pp. 215–219, 2011.
  18. J. Mahmod and M. Hicks, “Invisible bits: Hiding secret messages in sram’s analog domain,” in Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, ser. ASPLOS ’22.   New York, NY, USA: Association for Computing Machinery, 2022, p. 1086–1098.
  19. A. Srinivasan, J. Wu, P. Santhalingam, and J. Zamanski, “Deaddrop-in-a-flash: Information hiding at ssd nand flash memory physical layer,” SECURWARE, vol. 79, p. 2014, 2014.
  20. S. Jia, L. Xia, B. Chen, and P. Liu, “Deftl: Implementing plausibly deniable encryption in flash translation layer,” in Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security, 2017, pp. 2217–2229.
  21. P. R. Prucnal, M. P. Fok, K. Kravtsov, and Z. Wang, “Optical steganography for data hiding in optical networks,” in 2009 16th International Conference on Digital Signal Processing, 2009, pp. 1–6.
  22. K. Szczypiorski and W. Mazurczyk, “Steganography in ieee 802.11 ofdm symbols,” Security and Communication Networks, vol. 9, no. 2, pp. 118–129, 2016.
  23. A. M. Mehta, S. Lanzisera, and K. S. J. Pister, “Steganography in 802.15.4 wireless communication,” in International Symposium on Advanced Networks and Telecommunication Systems, 2008, pp. 1–3.
  24. N. F. Johnson and S. Jajodia, “Exploring steganography: Seeing the unseen,” Computer, vol. 31, no. 2, pp. 26–34, 1998.
  25. M. Borza, “Counterfeit chips 101: Protect your next design,” nov 2021, 18 November, 2021. [Online]. Available: https://blogs.synopsys.com/from-silicon-to-software/2021/11/02/what-are-counterfeit-chips/
  26. Y. Chen, “ReRAM : History, status, and future,” IEEE Transactions on Electron Devices, vol. 67, no. 4, pp. 1420–1433, 2020.
  27. D. Wei, L. Deng, P. Zhang, L. Qiao, and X. Peng, “Nrc: A nibble remapping coding strategy for nand flash reliability extension,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 11, pp. 1942–1946, 2016.
  28. W. Feng, H. Shima, K. Ohmori, and H. Akinaga, “Investigation of switching mechanism in hfox-reram under low power and conventional operation modes,” Scientific reports, vol. 6, no. 1, p. 39510, 2016.
  29. F. Koushanfar, I. Hong, and M. Potkonjak, “Behavioral synthesis techniques for intellectual property protection,” ACM Trans. Des. Autom. Electron. Syst., vol. 10, no. 3, p. 523–545, jul 2005.
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