Unifying Static and Dynamic Intermediate Languages for Accelerator Generators
Abstract: Compilers for accelerator design languages (ADLs) translate high-level languages into application-specific hardware. ADL compilers rely on a hardware control interface to compose hardware units. There are two choices: static control, which relies on cycle-level timing; or dynamic control, which uses explicit signalling to avoid depending on timing details. Static control is efficient but brittle; dynamic control incurs hardware costs to support compositional reasoning. Piezo is an ADL compiler that unifies static and dynamic control in a single intermediate language (IL). Its key insight is that the IL's static fragment is a refinement of its dynamic fragment: static code admits a subset of the run-time behaviors of the dynamic equivalent. Piezo can optimize code by combining facts from static and dynamic submodules, and it opportunistically converts code from dynamic to static control styles. We implement Piezo as an extension to an existing dynamic ADL compiler, Calyx. We use Piezo to implement an MLIR frontend, a systolic array generator, and a packet-scheduling hardware generator to demonstrate its optimizations and the static-dynamic interactions it enables.
- C Scott Ananian. Silicon C: A hardware backend for SUIF, May 1998. https://flex.cscott.net/SiliconC/.
- Stepwise debugging for hardware accelerators. In Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2023.
- Cadence. Stratus high-level synthesis. https://www.cadence.com/content/cadence-www/global/en_US/home/tools/digital-design-and-signoff/synthesis/stratus-high-level-synthesis.html.
- LegUp: High-level synthesis for FPGA-based processor/accelerator systems. In International Symposium on Field-Programmable Gate Arrays (FPGA), 2011.
- Balancing static islands in dynamically scheduled circuits using continuous petri nets. IEEE Transactions on Computers, 2023.
- Combining dynamic & static scheduling in high-level synthesis. In International Symposium on Field-Programmable Gate Arrays (FPGA), 2020.
- Finding and finessing static islands in dynamically scheduled circuits. In International Symposium on Field-Programmable Gate Arrays (FPGA), 2022.
- PolySA: Polyhedral-based systolic array auto-compilation. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2018.
- Robert Dockins. Operational refinement for compiler correctness. PhD thesis, Princeton University, 2012.
- Type-directed scheduling of streaming accelerators. In ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2020.
- Using deep programmability to put network owners in control. SIGCOMM Comput. Commun. Rev., 2020.
- A configurable cloud-scale DNN processor for real-time AI. In International Symposium on Computer Architecture (ISCA), 2018.
- Sergi Granell Escalfet. Accelerating halide on an FPGA. Master’s thesis, Universitat Politècnica de Catalunya, 2023.
- Darkroom: Compiling high-level image processing code into hardware pipelines. ACM Trans. Graph., 2014.
- Intel. oneAPI deep neural network library developer guide and reference. https://oneapi-src.github.io/oneDNN/.
- Intel. Intel High Level Synthesis Compiler. https://www.altera.com/products/design-software/high-level-design/intel-hls-compiler/overview.html, 2021.
- Dynamically scheduled high-level synthesis. In International Symposium on Field-Programmable Gate Arrays (FPGA), 2018.
- In-datacenter performance analysis of a Tensor Processing Unit. In International Symposium on Computer Architecture (ISCA), 2017.
- Spatial: A language and compiler for application accelerators. In ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2018.
- Hsiang-Tsung Kung. Why systolic architectures? IEEE Computer, 1982.
- HeteroCL: A multi-paradigm programming infrastructure for software-defined reconfigurable computing. In International Symposium on Field-Programmable Gate Arrays (FPGA), 2019.
- LLVM: A compilation framework for lifelong program analysis & transformation. In International Symposium on Code Generation and Optimization (CGO), 2004.
- MLIR: Scaling compiler infrastructure for domain specific computation. In International Symposium on Code Generation and Optimization (CGO), 2021.
- Louis-Noel Pouchet. PolyBench/C: The Polyhedral Benchmark Suite. http://web.cse.ohio-state.edu/~pouchet.2/software/polybench/, 2021.
- Rectifier nonlinearities improve neural network acoustic models. In International Conference on Machine Learning (ICML), 2013.
- HIR: An MLIR-based intermediate representation for hardware accelerator description. In ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2024.
- Mentor Graphics. Catapult high-level synthesis. https://www.mentor.com/hls-lp/catapult-high-level-synthesis/, 2021.
- Formal abstractions for packet scheduling. Proc. ACM Program. Lang., 7(OOPSLA2), 2023.
- Quantifying the cost and benefit of latency insensitive communication on FPGAs. In International Symposium on Field-Programmable Gate Arrays (FPGA), 2014.
- Predictable accelerator design with time-sensitive affine types. In ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2020.
- Modular hardware design with timeline types. In ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2023.
- A compiler infrastructure for accelerator generators. In ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2021.
- Bambu: A modular framework for the high level synthesis of memory-intensive applications. In International Conference on Field-Programmable Logic and Applications (FPL), 2013.
- Programming heterogeneous systems from an image processing DSL. ACM Trans. Archit. Code Optim., 2017.
- Halide: A language and compiler for optimizing parallelism, locality, and recomputation in image processing pipelines. In ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2013.
- AHIR: A hardware intermediate representation for hardware generation from high-level programs. In International Conference on VLSI Design (VLSID), 2007.
- μ𝜇\muitalic_μir: An intermediate representation for transforming and optimizing the microarchitecture of application accelerators. In IEEE/ACM International Symposium on Microarchitecture (MICRO), 2019.
- synASM: A high-level synthesis framework with support for parallel and timed constructs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012.
- Programmable packet scheduling at line rate. In Proceedings of the 2016 ACM SIGCOMM Conference, SIGCOMM ’16, New York, NY, USA, 2016. Association for Computing Machinery.
- Compiler discovered dynamic scheduling of irregular code in high-level synthesis. In International Conference on Field-Programmable Logic and Applications (FPL), 2023.
- The Calyx Authors. Compress static FSMs. https://github.com/cucapra/calyx/issues/936, 2023.
- The Calyx Authors. Fix top-down static timing. https://github.com/cucapra/calyx/pull/1338, 2023.
- The Calyx Authors. Problems with static FSMs. https://github.com/cucapra/calyx/issues/940, 2023.
- HLS from PyTorch to System Verilog with MLIR and CIRCT. In Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE), 2022.
- Veripool. Verilator, 2021. https://www.veripool.org/wiki/verilator.
- Hector: A multi-level intermediate representation for hardware synthesis methodologies. In International Conference On Computer Aided Design (ICCAD), 2022.
- Building a reusable and extensible automatic compiler infrastructure for reconfigurable devices. In International Conference on Field-Programmable Logic and Applications (FPL), 2023.
- AutoPilot: A platform-based ESL synthesis system. In High-Level Synthesis. 2008.
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