Unlocking High Performance, Ultra-Low Power Van der Waals Transistors: Towards Back-End-of-Line In-Sensor Machine Vision Applications

Abstract: Recent reports on ML and machine vision (MV) devices have demonstrated the potentials of 2D materials and devices. Yet, scalable 2D devices are being challenged by contact resistance and Fermi Level Pinning (FLP), power consumption, and low-cost CMOS compatible lithography processes. To enable CMOS+2D, it is essential to find a proper lithography strategy that can fulfill these requirements. Here, we explore modified van der Waals (vdW) deposition lithography and demonstrate a relatively new class of van-der-Waals-Field-Effect-Transistors (vdW-FETs) based on 2D materials. This lithography strategy enables us to unlock high performance devices evident by high current on-off ratio (Ion/Ioff), high turn-on current density (Ion), and weak Fermi Level Pinning (FLP). We utilize this approach to demonstrate a gate-tunable near-ideal diode using MoS2/WSe2 heterojunction with an ideality factor of ~1.65 and current rectification of 102. We finally demonstrate a highly sensitive, scalable, and ultra-low power phototransistor using MoS2/ WSe2 vdW-FET for Back-End-of-Line (BEOL) integration. Our phototransistor exhibits the highest gate-tunable photoresponsivity achieved to date for white light detection with ultra-low power dissipation, enabling ultra-sensitive, ultra-fast, and efficient optoelectronic applications such as in-sensor neuromorphic machine vision. Our approach shows the great potential of modified vdW deposition lithography for back-end-of-line CMOS+2D applications.