Optimizing the Efficiency of Accelerated Reliability Testing for the Internet Router Motherboard

Abstract: With the rapid development of internet Router, the complexity of its mainboard has been growing dramatically. The high reliability requirement renders the number of testing cases increasing exponentially, which becomes the bottleneck that prevents further elevation of the production efficiency. In this work, we develop a novel optimization method of two major steps to largely reduce the testing time and increase the testing efficiency. In the first step, it optimizes the selection of test cases given the required amount of testing time reduction while ensuring the coverage of failures. In the second step, selected test cases are optimally scheduled to maximize the efficiency of mainboard testing. A numerical experiment is investigated to illustrate the effectiveness of the proposed methods. The results show that the optimal subset of the test cases can be selected satisfying the 10% testing time reduction requirement, and the effectiveness index of the scheduled sequence can be improved by more than 75% with test case sequencing. Moreover, our method can self-adjust to the new failure data, which realizes the automatic configuration of board test cases.