Charge pump phase-locked loop with phase-frequency detector: closed form mathematical model

Abstract: Charge pump phase-locked loop with phase-frequency detector (CP-PLL) is an electrical circuit, widely used in digital systems for frequency synthesis and synchronization of the clock signals. In this paper a non-linear second-order model of CP-PLL is rigorously derived. The obtained model obviates the shortcomings of previously known second-order models of CP-PLL. Pull-in time is estimated for the obtained second-order CP-PLL.