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A Many-Core Overlay for High-Performance Embedded Computing on FPGAs (1408.5401v1)
Published 21 Aug 2014 in cs.AR
Abstract: In this work, we propose a configurable many-core overlay for high-performance embedded computing. The size of internal memory, supported operations and number of ports can be configured independently for each core of the overlay. The overlay was evaluated with matrix multiplication, LU decomposition and Fast-Fourier Transform (FFT) on a ZYNQ-7020 FPGA platform. The results show that using a system-level many-core overlay avoids complex hardware design and still provides good performance results.
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