Sub-micrometer epitaxial Josephson junctions for quantum circuits

Abstract: We present a fabrication scheme and testing results for epitaxial sub-micrometer Josephson junctions. The junctions are made using a high-temperature (1170 K) "via process" yielding junctions as small as 0.8 mu m in diameter by use of optical lithography. Sapphire (Al2O3) tunnel-barriers are grown on an epitaxial Re/Ti multilayer base-electrode. We have fabricated devices with both Re and Al top electrodes. While room-temperature (295 K) resistance versus area data are favorable for both types of top electrodes, the low-temperature (50 mK) data show that junctions with the Al top electrode have a much higher subgap resistance. The microwave loss properties of the junctions have been measured by use of superconducting Josephson junction qubits. The results show that high subgap resistance correlates to improved qubit performance.

• The paper introduces a novel high-temperature via process that fabricates sub-μm epitaxial Josephson junctions with precise atomic-scale tunnel barriers.
• The paper demonstrates that Al top-electrode junctions yield high subgap resistance and superior qubit coherence (T1=500 ns) compared to Re top-electrodes.
• The paper employs optimized patterning and in situ cleaning techniques, ensuring smooth base-electrode surfaces for scalable integration in complex superconducting circuits.

This paper (1108.1830) presents a fabrication method for sub-micrometer epitaxial Josephson junctions with Al$_2$O$_3$ tunnel barriers, specifically designed for superconducting quantum circuits. The primary motivation is to address the issue of decoherence in superconducting qubits caused by two-level systems (TLS) located in the amorphous AlO$_x$ tunnel barriers typically used. Previous work had shown that reducing junction area or using epitaxial barriers could improve coherence, but a method combining both was needed, especially one compatible with optical lithography and complex circuit designs including cross-overs.

The authors developed a high-temperature "via process" to achieve sub-micrometer epitaxial junctions. The process starts with a single-crystal Al$_2$O$_3$(0001) sapphire substrate, which is furnace-annealed at 1370 K to improve surface crystallinity and form atomic step terraces. A smooth, epitaxial base-electrode is crucial, and the authors found that a (Re/Ti)$_{12}$Re multilayer film sputtered at 1170 K yields significantly lower root mean square (rms) roughness (0.6 nm) compared to a pure Re film (3.2 nm) (1108.1830). This smoother surface is more favorable for subsequent tunnel-barrier growth.

The key steps of the via process are:

1. Patterning the (Re/Ti)$_{12}$Re base-electrode using RIE.
2. Depositing a cross-over insulator (SiO$_x$ or SiN$_x$) via plasma enhanced chemical vapor deposition at room temperature.
3. Etching vias through the insulator down to the base-electrode using RIE. This step defines the junction size and shape. Laser interferometer endpoint detection is used to minimize over-etching into the base-electrode.
4. Loading the wafer back into a UHV sputter tool. The base-electrode surface in the via is cleaned via an argon RF-clean to remove approximately 2 nm of material, and then annealed at 1170 K for 1 hour to recrystallize the surface damaged by the etch.
5. In situ growth of the epitaxial Al$_2$O$_3$ tunnel-barrier by UHV RF magnetron-sputtering from a sintered Al$_2$O$_3$ target at 1170 K, with added oxygen to maintain stoichiometry. Barrier thickness ($1.8 \pm 0.2$ nm) is monitored by spectroscopic ellipsometry.
6. Cooling the wafer to room temperature and in situ deposition of the top-electrode (either Re or Al) by UHV DC magnetron-sputtering. Xenon gas is used for Re sputtering to minimize energetic neutrals.
7. Patterning the top-electrode (RIE for Re, argon ion mill for Al).

The process yields junctions with a process bias of -0.3 $\mu$m, meaning they are 0.3 $\mu$m larger than designed (1108.1830). For example, a 0.5 $\mu$m designed junction measured 0.8 $\mu$m in diameter.

Electrical characterization revealed important differences between junctions with Re and Al top-electrodes:

• Room Temperature (295 K): Both Re and Al top-electrode junctions showed flat resistance x area (RA) product vs. electrical area for medium and large sizes, indicating no significant perimeter transport (1108.1830). Based solely on room-temperature data, both appeared suitable.
• Low Temperature (50 mK): A dramatic difference was observed in the subgap structure. Re top-electrode junctions exhibited low subgap resistance ($R_{sg}$) – only about 5 times the normal-state resistance – indicating non-tunnelling transport mechanisms. In contrast, Al top-electrode junctions showed sharp IV curves with high subgap resistance and re-trapping current limited by noise, characteristic of high-quality tunnel junctions (1108.1830). This qualitative difference was consistent across multiple wafers and junction sizes. The measured superconducting gaps agreed with BCS theory.

To evaluate the impact on qubit performance, phase qubits with Re top-electrodes and transmon qubits with Al top-electrodes were fabricated and measured.

• A phase qubit with a Re top-electrode junction (nominally 4 $\mu$m$^2$) had a short energy relaxation time ($T_1$) of only 15 ns (1108.1830). This was hypothesized to be limited by the low subgap resistance of the junction, with a classical $RC$ decay time of $\sim 2$ ns.
• A transmon qubit with Al top-electrode junctions (two 1 $\mu$m$^2$ junctions total area $\sim 2$ $\mu$m$^2$) showed a significantly longer $T_1$ of 500 ns (1108.1830). This qubit was not limited by the Purcell effect. Spectroscopy revealed several TLS splittings, but the coherence was much better than the Re-based device.

A loss analysis for the Al top-electrode transmon using participation ratios indicated that the junction and interdigitated capacitor (IDC) were the primary contributors to the total loss, which correlated with the measured $T_1$. This suggests that while the epitaxial barrier in the junction is better than amorphous AlO$_x$, it is still a significant source of loss, as is the IDC. The SiN$_x$ insulator contributed much less to the total loss.

The authors concluded that the via process successfully enables the fabrication of sub-micrometer epitaxial junctions. Crucially, junctions with Al top-electrodes exhibit high subgap resistance and result in significantly better qubit coherence ($T_1=500$ ns) compared to those with Re top-electrodes ($T_1=15$ ns). This supports the hypothesis that the interface between the Al$_2$O$_3$ tunnel barrier and the top electrode plays a significant role in determining junction quality and qubit coherence, with the Al-Al$_2$O$_3$ interface being superior to the Re-Al$_2$O$_3$ interface in this context. While the achieved $T_1$ for the Al top-electrode transmon (500 ns) was not as long as the best reported amorphous-barrier transmons at the time (2000 ns), the method represents a step towards realizing high-coherence epitaxial junctions suitable for complex, optically-defined quantum circuits.