- The paper demonstrates that DARC achieves low latency (100–220 μs) and low jitter (6–11 μs) using a horizontal processing strategy on COTS CPUs.
- The system features modular components, hot-swappable reconstruction modules, and versatile I/O interfaces, including optional FPGA acceleration.
- Performance validation in lab and on-sky setups confirms DARC’s suitability for advanced AO applications with high frame rates on large telescopes.
Introduction
This paper presents the Durham adaptive optics real-time controller (DARC), a flexible and high-performance CPU-based platform for AO real-time control. DARC was initially conceived as a generic proof-of-concept but has matured into a robust and extensible architecture, capable of multi-threaded operation on modern off-the-shelf hardware, supporting GPU and FPGA acceleration where required. Unlike earlier AO control systems, which relied heavily on dedicated hardware (with concomitant obsolescence and inflexibility), DARC is explicitly designed for hardware-agnostic deployment, supporting current and future 8–10 m class telescope AO configurations.
System Architecture and Software Pipeline
DARC comprises several modular components: the real-time control pipeline (RTCP), control interface, diagnostic subsystem, graphical/scripting interfaces, and various background processes. Central to DARC is the RTCP, handling wavefront sensor (WFS) pixel stream ingestion, calibration, slope calculation, wavefront reconstruction, and generation of deformable mirror (DM) actuator command vectors.
A distinguishing feature of DARC is its "horizontal processing strategy," which contrasts with conventional "vertical" pipelining. In the horizontal approach, available threads perform all algorithmic stages for sub-apertures as soon as their pixels are available, thus minimizing systemic latency. This leads to superior CPU utilization and reduced inter-thread synchronization overhead, yielding strong determinism and low jitter in AO loop closure computations.
The RTCP design is agnostic with respect to input and output interfaces, supporting, for example, sFPDP, Ethernet, custom socket, and direct file modes. Plug-in libraries allow real-time swapping of interfaces for both sensor ingestion and mirror command emission without system downtime. The wavefront reconstruction module is similarly hot-swappable, supporting matrix-vector multiplication, Kalman filtering, and Fourier-based reconstructor implementations.
An optional FPGA-based WFS front-end provides deterministic, low-latency (<1 μs) slope computation, enabling the RTCP CPU to focus on high-order reconstruction, further reducing per-frame computation time for large-scale AO systems.
Algorithmic Capabilities
DARC implements standard and advanced calibration (background subtraction, flat-fielding, pixel weighting) and centroiding (standard/weighted center-of-gravity, correlation) methods. For control, it features integrator laws, open- and closed-loop operation (supporting multi-object adaptive optics, MOAO), and a figure sensor feedback mechanism for non-linear DM compensation—a key enabler for high-precision open-loop systems.
Slope linearization (with per sub-aperture lookup tables) is available, particularly relevant for open-loop compensation or elongated laser guide star spot images. Two adaptive windowing modes further mitigate spot motion errors by dynamically tracking local or global image shifts per sub-aperture.
Performance metrics are expressed in terms of system latency (interval between last WFS pixel arrival and DM command emission) and temporal jitter. Hardware measurements using high-speed oscilloscopes demonstrate that, using COTS multi-core CPUs (e.g., quad quad-core Opteron or Xeon from 2008–2009 generations), DARC achieves latencies as low as 100–220 μs and temporal jitter of 6–11 μs for typical laboratory and on-sky AO configurations with 7×7 sub-apertures and 52-actuator DMs.
Crucially, when leveraging the FPGA WFS front-end, DARC's maximum computed frame rates reach beyond 2 kHz for 64×64 sub-aperture systems with over 3000 actuators—performance requirements suitable for extreme AO and planet-finding instrument scenarios on Class 8 m telescopes. Jitter remains bounded and non-Gaussian but does not display sporadic catastrophic outliers, ensuring system stability even under demanding closed-loop conditions.
For advanced MOAO deployments, such as the CANARY instrument, DARC demonstrates measured latencies of 245 ±11 μs over three WFS channels and 52-actuator DM, well within operational requirements. Open-loop performance is further validated by laboratory and on-sky imaging, yielding H-band Strehl ratios near 26%.
The figure sensing subsystem, running asynchronously, is validated to introduce little additional overhead (measured latency of 70±5 μs), and closed-loop compensator iteration performance matches expectations analytically derived from the timing diagrams.
Notably, DARC numerically matches or surpasses legacy bespoke hardware platforms (such as ESA SPARTA), deploying high-order AO control entirely in software with commodity components.
Architectural Implications and Future Directions
DARC represents a shift in AO control paradigm toward modular, open, and software-centric platforms. The demonstrated performance removes the necessity for expensive, complex hardware solutions for essentially all 8–10 m class AO systems. The generic interface layers for input, output, and reconstruction enable rapid prototyping, testing, and upgrades, insulating the AO system from hardware churn and facilitating technology evolution.
The system's capacity for dynamic reconfiguration (e.g., hot-swapping reconstruction kernels or data interfaces during operation) aligns with contemporary trends towards software-defined instrumentation and autonomous system optimization. DARC enables background processes such as atmospheric turbulence profiling, real-time control matrix optimization, and advanced telemetry, paving the way for closed-loop control software that is adaptive not only to current observing conditions but also to underlying hardware performance.
Advancing the system with support for asynchronous and multi-rate WFS integration (not yet implemented as of this report), as well as further leveraging hardware acceleration (multi-GPU/FPGA scaling), positions DARC as a candidate baseline for emerging ELT-class AO systems and as a robust platform for experimental AO algorithm development.
Conclusion
DARC establishes that modern CPU-based real-time controllers, leveraging horizontal multithreaded processing on COTS hardware, can reliably achieve low-latency and low-jitter operation for high-order AO systems, with direct applicability to science-grade instruments on large telescopes. The architecture’s modularity, hot-swap capabilities, and detached diagnostic and control interfaces yield substantial operational flexibility.
The empirical demonstration that entirely CPU-based (and optionally FPGA-accelerated) software can replace complex bespoke hardware in demanding astronomical AO settings challenges prevailing practices and supports the wider adoption of generic, reconfigurable software stacks in real-time hardware-in-the-loop scientific control.
Anticipated developments include support for asynchronous WFS operation and expanded use of hardware accelerators. Overall, DARC’s design and measured performance underscore the maturity and readiness of software-centric AO control for both current and future astronomical instrumentation.