Explain the interaction causing x264 performance behavior across CPU sizes

Determine a full mechanistic explanation of the interaction between instruction window scaling and Store Sets memory dependence predictor table size (SSIT and LFST) that produces larger performance gains for the Spec2017 benchmark 625.x264_s on the large Gem5 CPU model but not on the small or extra-large models when using LLVM-emitted "Predict No Dependency" (PND) load opcodes, specifically characterizing how additional behavior captured by larger instruction windows relates to index collisions in the Store Sets predictor.

Background

The paper proposes compiler-driven "Predict No Dependency" (PND) load labels that bypass the Memory Dependence Predictor (MDP) to reduce false dependencies, particularly those arising from Store Sets index collisions. Using Gem5 simulations across three CPU models (small, large, extra-large), the authors observe notable performance gains in certain benchmarks.

For 625.x264_s, the large CPU model exhibits larger gains than the small model, with gains lost again in the extra-large model. The authors partially attribute losses to MDP size and suspect additional behavior captured by larger instruction windows relates to index collisions, but they cannot fully explain the interaction. Clarifying this mechanism is important for understanding and generalizing the performance effects of PND labels.