Compare SFAFFT with existing AVX-512 HQC implementations

Compare the Strided Frobenius Additive FFT (SFAFFT) implementation for HQC with existing AVX-512 HQC multiplication implementations under the same experimental conditions, once the SFAFFT source code is available.

Background

The paper discusses the Strided Frobenius Additive FFT (SFAFFT), which reduces the number of butterfly stages and uses products over smaller quotient rings. Existing SFAFFT implementations target AVX2, GFNI, Apple M1, and Arm processors, but do not include AVX-512.

A direct comparison with the paper’s AVX-512 implementations remains unresolved because the SFAFFT source code was unavailable. Such a comparison would require implementing or obtaining an AVX-512 version and evaluating it under the same hardware, parameter sets, and measurement methodology.

References

The authors state that the source code will be released. Since it is currently unavailable, we leave a comparison under the same experimental conditions for future work.

— Accelerating HQC for Post-Quantum TLS 1.3 on x86 IoT Gateways  (2610.11107 - Jang et al., 8 Oct 2026) in Section 1, Related Works