Frequency-Multiplexed Millimeter-Wave Fault-Tolerant Superconducting Qubits Enabled by an On-Chip Nonreciprocal Control Bus (2512.17588v1)

Abstract: Scaling superconducting quantum processors is fundamentally limited by the escalating complexity of cryogenic wiring and the debilitating effects of microwave crosstalk and Purcell decay. This paper proposes the concept of frequency-multiplexed millimeter-wave superconducting qubits and demonstrates a novel architecture that integrates an on-chip cryogenic nonreciprocal space-time-periodic superconducting frequency multiplier as a universal control bus for a frequency-multiplexed qubit array. The bus replaces multiple high-frequency XY drive lines with a single low-frequency input tone, which the multiplier converts into a comb of high-order harmonics, each resonantly addressing a distinct qubit. Crucially, the dynamic and nonreciprocal nature of the bus provides signal gain and intrinsic isolation that simultaneously suppresses Purcell decay, enhancing T1 times across all distinct-frequency qubits, and reduces coherent crosstalk by more than two orders of magnitude. The spatiotemporal modulation enables parametric frequency multiplication and creates wave-propagation dynamics analogous to cosmological expansion, with observed redshift-like broadening and deceleration of magnetic-field wavepackets. Theoretical modeling based on a non-Markovian master equation confirms that the engineered memory kernel extends coherence while reshaping the noise spectrum. Full error-budget analysis shows that the architecture maintains gate errors below the fault-tolerance threshold for arrays exceeding 25 qubits, converting a crosstalk-dominated error budget into one limited by intrinsic material coherence. This integrated, frequency-multiplexed, and nonreciprocal control bus therefore offers a path toward unprecedented I/O simplification, noise resilience, and scalable high-coherence quantum processin