Automated Multi-Agent Workflows for RTL Design (2509.20182v1)

Abstract: The rise of agentic AI workflows unlocks novel opportunities for computer systems design and optimization. However, for specialized domains such as program synthesis, the relative scarcity of HDL and proprietary EDA resources online compared to more common programming tasks introduces challenges, often necessitating task-specific fine-tuning, high inference costs, and manually-crafted agent orchestration. In this work, we present VeriMaAS, a multi-agent framework designed to automatically compose agentic workflows for RTL code generation. Our key insight is to integrate formal verification feedback from HDL tools directly into workflow generation, reducing the cost of gradient-based updates or prolonged reasoning traces. Our method improves synthesis performance by 5-7% for pass@k over fine-tuned baselines, while requiring only a few hundred training examples, representing an order-of-magnitude reduction in supervision cost.

• The paper demonstrates that VeriMaAS improves RTL synthesis accuracy by up to 7–12% while reducing fine-tuning needs.
• It employs a cascading strategy with adaptive multi-agent operators that leverage formal verification feedback for dynamic operator selection.
• Experimental results reveal significant gains in pass@1/pass@10 metrics and PPA optimization, underscoring its practical efficiency.

Automated Multi-Agent Workflows for RTL Design: The VeriMaAS Framework

Introduction

The paper presents VeriMaAS, a multi-agent orchestration framework for register-transfer level (RTL) code generation, targeting the synthesis and verification of hardware designs. The approach leverages agentic AI workflows, integrating formal verification feedback from hardware description language (HDL) tools directly into the workflow generation process. This integration enables dynamic refinement of agentic operator selection, reducing the need for extensive fine-tuning and minimizing inference costs. The framework is evaluated on state-of-the-art RTL benchmarks, demonstrating improved synthesis accuracy and efficiency compared to both fine-tuned and single-agent prompting baselines.

Figure 1: VeriMaAS workflow: adaptive sampling of agentic operators for RTL tasks, with formal verification and synthesis feedback guiding dynamic operator selection.

Methodology

VeriMaAS operates by adaptively sampling a set of agentic reasoning operators—Zero-shot I/O, Chain-of-Thought (CoT), ReAct, Self-Refine, and Debate—based on the input RTL query and its difficulty. The multi-agent solution space $\mathbb{O}$ is composed of these operators, and the controller $\mathcal{C}$ dynamically selects operator sequences for each task. Candidate Verilog designs generated at each stage are synthesized and verified using Yosys and OpenSTA, with synthesis logs and error messages serving as feedback to inform subsequent operator selection.

The controller employs a cascading strategy, progressing through increasingly complex operators. At each stage, a confidence score $s_c$ is computed as the percentage of failing designs (due to synthesis or verification errors). If $s_c$ exceeds a stage-specific threshold $\tau_c$, the controller escalates to the next operator; otherwise, it terminates and returns the current solution set. Thresholds are learned via multi-objective optimization, balancing pass@k utility against token cost, and are tuned using a few hundred examples—an order-of-magnitude reduction in supervision compared to full model fine-tuning.

Experimental Results

VeriMaAS is evaluated on the VeriThoughts and VerilogEval benchmarks, using Yosys for synthesis and area estimation, and OpenSTA for timing and power analysis. The framework is tested with both proprietary and open-weight LLMs, as well as fine-tuned RTL models. Performance is measured using pass@1 and pass@10 metrics over 20 samples per query.

Key findings include:

• Accuracy Gains: VeriMaAS yields up to 7–12% improvement in pass@1 over fine-tuned baselines for open-source LLMs, and consistent gains in pass@10, expanding the pool of valid candidate designs.
• Token Efficiency: The framework maintains moderate token overhead, comparable to lightweight CoT prompting and significantly lower than iterative strategies like Self-Refine.
• Closed-Source Models: Gains are smaller but consistent, indicating that multi-agent orchestration provides value even when base model performance is high.
• PPA-Aware Optimization: By re-optimizing the controller for post-synthesis metrics (area, power, delay), VeriMaAS achieves up to 28.79% area reduction and notable improvements in runtime, with some trade-offs in power and pass@10.

Implications and Future Directions

VeriMaAS demonstrates that integrating formal verification feedback into agentic workflow generation can substantially improve RTL synthesis accuracy and efficiency, while reducing the need for costly fine-tuning. The framework's modular controller allows for flexible optimization of different design objectives, such as power, performance, and area (PPA), without entangling these goals in model weights.

The approach suggests several avenues for future research:

• Controller Enhancement: Incorporating tree-search or RL-based policies could further improve operator selection and workflow efficiency.
• EDA Tool Integration: Expanding orchestration signals to commercial EDA tools and process design kits (PDKs) would enable more comprehensive synthesis and PPA optimization.
• Generalization: The methodology could be extended to other domains requiring formal verification and multi-agent reasoning, such as analog design or system-level hardware synthesis.

Conclusion

VeriMaAS introduces a principled multi-agent framework for RTL code generation, leveraging formal verification feedback to guide agentic workflow composition. The method achieves strong numerical improvements in synthesis accuracy and efficiency, with minimal supervision cost. Its flexible controller design and integration with EDA tools position it as a promising direction for automated hardware design and optimization. Future work will focus on enhancing controller policies and expanding integration with commercial synthesis flows to further advance agentic AI for hardware systems design.