- The paper demonstrates that Omni 3D integrates BEOL-compatible transistors with interleaved metal layers to enable fine-grained and double-side routing.
- It achieves a 2.0x improvement in energy-delay product and a 1.5x reduction in area compared to state-of-the-art CFET designs.
- The methodology employs a virtual-source BEOL-FET compact model and DTCO to optimize multiple architecture variants for high-performance electronic systems.
The paper "Omni 3D: BEOL-Compatible 3D Logic with Omnipresent Power, Signal, and Clock" introduces a novel 3D-stacked device architecture named Omni 3D. This architecture is characterized by the use of back-end-of-line (BEOL)-compatible transistors, which include fully integrated metal layers for both signal and power distribution interwoven with field-effect transistors (FETs) in multiple layers. Unlike other approaches such as back-side power delivery networks (BSPDNs), complementary FETs (CFETs), and traditional stacked FETs, Omni 3D offers greater flexibility in 3D standard cell design due to its ability to interleave metal and transistor layers.
Key Features of Omni 3D
- Fine-Grained Routing: Omni 3D allows for fine-grained access to active regions of nFETs and pFETs, maximizing routing flexibility. This is achieved by interleaving metal layers with FET layers, enabling signal and power routing from all sides.
- Double-Side Routing: The architecture features double-side routing and an interleaved metal (IM) layer that facilitates both inter- and intra-cell routing. This provides substantial enhancements over conventional routing methods by offering more efficient routing paths and reducing congestion.
- Variants and Optimization: The paper explores different variants of the Omni 3D architecture, both with and without the IM layer. These variants are optimized using a virtual-source BEOL-FET compact model to ensure high performance and efficiency.
- Design-Technology Co-Optimization (DTCO): A thorough DTCO is performed for the Omni 3D architecture across several design points. This involves establishing a specialized physical design flow that effectively leverages the unique routing capabilities of Omni 3D.
The authors project significant improvements in key performance metrics for the Omni 3D architecture compared to state-of-the-art CFETs with BSPDNs. Specifically, they estimate:
- 2.0x Improvement in Energy-Delay Product (EDP): This indicates that the Omni 3D architecture can potentially double the efficiency of computational tasks, balancing both energy consumption and processing speed.
- 1.5x Reduction in Area: The architecture promises to halve the physical footprint of circuits, which is critical for the continued scaling of electronic devices.
Conclusion
Omni 3D represents a substantial advancement in 3D-stacked device architectures by marrying the advantages of BEOL-compatible transistors with innovative routing solutions. The enhanced flexibility and performance projections make it a promising contender for future high-performance, energy-efficient electronic designs.