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Complete Boolean Algebra for Memristive and Spintronic Asymmetric Basis Logic Functions (2404.17068v1)

Published 25 Apr 2024 in cs.ET

Abstract: The increasing advancement of emerging device technologies that provide alternative basis logic sets necessitates the exploration of innovative logic design automation methodologies. Specifically, emerging computing architectures based on the memristor and the bilayer avalanche spin-diode offer non-commutative or `asymmetric' operations, namely the inverted-input AND (IAND) and implication as basis logic gates. Existing logic design techniques inadequately leverage the unique characteristics of asymmetric logic functions resulting in insufficiently optimized logic circuits. This paper presents a complete Boolean algebraic framework specifically tailored to asymmetric logic functions, introducing fundamental identities, theorems and canonical normal forms that lay the groundwork for efficient synthesis and minimization of such logic circuits without relying on conventional Boolean algebra. Further, this paper establishes a logical relationship between implication and IAND operations. A previously proposed modified Karnaugh map method based on a subset of the presented algebraic principles demonstrated a 28% reduction in computational steps for an algorithmically designed memristive full adder; the presently-proposed algebraic framework lays the foundation for much greater future improvements.

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References (36)
  1. N. S. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Irwin, M. Kandemir, and V. Narayanan, “Leakage current: Moore’s law meets static power,” computer, vol. 36, no. 12, pp. 68–75, 2003.
  2. M. S. Lundstrom and M. A. Alam, “Moore’s law: The journey ahead,” Science, vol. 378, no. 6621, pp. 722–723, 2022.
  3. M. T. Bohr and I. A. Young, “Cmos scaling trends and beyond,” IEEE Micro, vol. 37, no. 6, pp. 20–29, 2017.
  4. M. M. Waldrop, “The chips are down for moore’s law,” Nature News, vol. 530, no. 7589, p. 144, 2016.
  5. G. Finocchio, J. A. C. Incorvia, J. S. Friedman, Q. Yang, A. Giordano, J. Grollier, H. Yang, F. Ciubotaru, A. Chumak, A. Naeemi et al., “Roadmap for unconventional computing with nanotechnology,” Nano Futures, 2023.
  6. W. Liu, P. K. J. Wong, and Y. Xu, “Hybrid spintronic materials: Growth, structure and properties,” Progress in Materials Science, vol. 99, pp. 27–105, 2019.
  7. X. Lin, W. Yang, K. L. Wang, and W. Zhao, “Two-dimensional spintronics for low-power electronics,” Nature Electronics, vol. 2, no. 7, pp. 274–283, 2019.
  8. D. M. Bromberg, D. H. Morris, L. Pileggi, and J.-G. Zhu, “Novel stt-mtj device enabling all-metallic logic circuits,” IEEE transactions on Magnetics, vol. 48, no. 11, pp. 3215–3218, 2012.
  9. J. S. Friedman and A. V. Sahakian, “Complementary magnetic tunnel junction logic,” IEEE Transactions on Electron Devices, vol. 61, no. 4, pp. 1207–1210, 2014.
  10. D. A. Allwood, G. Xiong, C. Faulkner, D. Atkinson, D. Petit, and R. Cowburn, “Magnetic domain-wall logic,” Science, vol. 309, no. 5741, pp. 1688–1692, 2005.
  11. K. Omari and T. Hayward, “Chirality-based vortex domain-wall logic gates,” Physical Review Applied, vol. 2, no. 4, p. 044001, 2014.
  12. P. Xu, K. Xia, C. Gu, L. Tang, H. Yang, and J. Li, “An all-metallic logic gate based on current-driven domain wall motion.” Nature nanotechnology, vol. 3, no. 2, 2008.
  13. A. Imre, G. Csaba, L. Ji, A. Orlov, G. H. Bernstein, and W. Porod, “Majority logic gate for magnetic quantum-dot cellular automata,” Science, vol. 311, no. 5758, pp. 205–208, 2006.
  14. J. S. Friedman, A. Girdhar, R. M. Gelfand, G. Memik, H. Mohseni, A. Taflove, B. W. Wessels, J.-P. Leburton, and A. V. Sahakian, “Cascaded spintronic logic with low-dimensional carbon,” Nature communications, vol. 8, p. 15635, 2017.
  15. B. W. Walker, A. J. Edwards, X. Hu, M. P. Frank, F. Garcia-Sanchez, and J. S. Friedman, “Near-landauer reversible skyrmion logic with voltage-based propagation,” arXiv preprint arXiv:2301.10700, 2023.
  16. S. Datta and B. Das, “Electronic analog of the electro-optic modulator,” Applied Physics Letters, vol. 56, no. 7, pp. 665–667, 1990.
  17. H. C. Koo, J. H. Kwon, J. Eom, J. Chang, S. H. Han, and M. Johnson, “Control of spin precession in a spin-injected field effect transistor,” Science, vol. 325, no. 5947, pp. 1515–1518, 2009.
  18. J. Schliemann, J. C. Egues, and D. Loss, “Nonballistic spin-field-effect transistor,” Physical review letters, vol. 90, no. 14, p. 146801, 2003.
  19. B. Wang, J. Wang, and H. Guo, “Quantum spin field effect transistor,” Physical Review B, vol. 67, no. 9, p. 092408, 2003.
  20. P. Barla, V. K. Joshi, and S. Bhat, “Spintronic devices: a promising alternative to cmos devices,” Journal of Computational Electronics, vol. 20, no. 2, pp. 805–837, 2021.
  21. J. S. Friedman, E. R. Fadel, B. W. Wessels, D. Querlioz, and A. V. Sahakian, “Bilayer avalanche spin-diode logic,” AIP Advances, vol. 5, no. 11, p. 117102, 2015.
  22. V. Vyas and J. S. Friedman, “Sequential circuit design with bilayer avalanche spin diode logic,” in Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018, pp. 49–50.
  23. S. Kvatinsky, A. Kolodny, U. C. Weiser, and E. G. Friedman, “Memristor-based imply logic design procedure,” in 2011 IEEE 29th International Conference on Computer Design (ICCD).   IEEE, 2011, pp. 142–147.
  24. S. Kvatinsky, G. Satat, N. Wald, E. G. Friedman, and U. C. Kolodny, A.and Weiser, “Memristor-based material implication (IMPLY) logic: Design principles and methodologies,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 10, pp. 2054–2066, 2014.
  25. A. Chattopadhyay and Z. Rakosi, “Combinational logic synthesis for material implication,” 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, pp. 200–203, 2011.
  26. A. Raghuvanshi and M. Perkowski, “Logic synthesis and a generalized notation for memristor-realized material implication gates,” in Proceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design, ser. ICCAD ’14.   Piscataway, NJ, USA: IEEE Press, 2014, pp. 470–477.
  27. E. Lehtonen, J. Poikonen, and M. Laiho, “Implication logic synthesis methods for memristors,” in 2012 IEEE International Symposium on Circuits and Systems, May 2012, pp. 2441–2444.
  28. S. Shirinzadeh, M. Soeken, and R. Drechsler, “Multi-objective BDD optimization for RRAM based circuit design,” in Formal Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2016, 2016.
  29. F. S. Marranghello, V. Callegaro, A. I. Reis, and R. P. Ribas, “SOP based logic synthesis for memristive IMPLY stateful logic,” in 2015 33rd IEEE International Conference on Computer Design (ICCD).   IEEE, oct 2015, pp. 228–235.
  30. S. Chakraborti, P. V. Chowdhary, K. Datta, and I. Sengupta, “Bdd based synthesis of boolean functions using memristors,” in Design & Test Symposium (IDT), 2014 9th International.   IEEE, 2014, pp. 136–141.
  31. F. Lalchhandama, B. G. Sapui, and K. Datta, “An improved approach for the synthesis of Boolean functions using memristor based IMPLY and INVERSE-IMPLY gates,” in 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), vol. 2016-Septe.   IEEE, jul 2016, pp. 319–324.
  32. D. Fan and K. Sharad, M.and Roy, “Design and synthesis of ultralow energy spin-memristor threshold logic,” IEEE Transactions on Nanotechnology, vol. 13, no. 3, pp. 574–583, 2014.
  33. V. Vyas, L. Jiang-Wei, P. Zhou, X. Hu, and J. S. Friedman, “Karnaugh map method for memristive and spintronic asymmetric basis logic functions,” IEEE Transactions on Computers, vol. 70, no. 1, pp. 128–138, 2020.
  34. L. Chua, “Memristor-the missing circuit element,” IEEE Transactions on Circuit Theory, vol. 18, no. 5, pp. 507–519, September 1971.
  35. D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, “The missing memristor found,” Nature, vol. 459, no. 7250, pp. 1154–1154, 2009.
  36. J. Borghetti, G. S. Snider, P. J. Kuekes, J. J. Yang, D. R. Stewart, and R. S. Williams, “’Memristive’ switches enable ’stateful’ logic operations via material implication,” Nature, vol. 464, no. 7290, pp. 873–876, 2010.

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