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32-Bit RISC-V CPU Core on Logisim (2312.01455v1)
Published 3 Dec 2023 in cs.AR
Abstract: This project focuses on making a RISC-V CPU Core using the Logisim software. RISC-V is significant because it will allow smaller device manufacturers to build hardware without paying royalties and allow developers and researchers to design and experiment with a proven and freely available instruction set architecture. RISC-V is ideal for a variety of applications from IOTs to Embedded systems such as disks, CPUs, Calculators, SOCs, etc. RISC-V(Reduced Instruction Set Architecture) is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use.
- Toms42. “Logisim RISC-V CPU.” GitHub. https://github.com/Toms42/logisim-RISC-V-CPU
- ninja3011. “8-bit-computer: Simulate and build Ben Eaters 8 Bit Computer.” GitHub. https://github.com/ninja3011/8bitcomputer
- ninja3011. “RISC-V pipelined core, housing a RV64I instruction set.” GitHub. https://github.com/ninja3011/riscv-cpu-core
- University of California, Berkeley. “EECS Instructional and Electronics Support.” https://inst.eecs.berkeley.edu/
- edX. “Building a RISC-V CPU Core.” https://learning.edx.org/course/course-v1:LinuxFoundationX+LFD111x+1T2021/home
- Eater, Ben. “Ben Eater” YouTube. https://www.youtube.com/@BenEater
- Siddesh D. Patil (1 paper)
- Premraj V. Jadhav (1 paper)
- Siddharth Sankhe (1 paper)