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Universal FSA Emulation by Neural Finite-State Machines

Updated 7 December 2025
  • Universal FSA Emulation is a method where finite-depth feedforward ReLU and threshold networks simulate any deterministic finite automaton by encoding state transitions for bounded-length inputs.
  • It employs explicit layerwise constructions, including one-hot and binary encodings with two-layer transition modules, to implement regular language recognition.
  • The approach demonstrates exponential state compression, latent embeddings of Myhill–Nerode equivalence classes, and a formal expressivity boundary for fixed-depth networks.

Universal finite-state automaton (FSA) emulation refers to the capacity of certain neural network architectures—specifically, finite-depth feedforward ReLU and threshold networks—to exactly simulate any deterministic finite automaton (DFA) on bounded-length inputs, thus acting as "neural finite-state machines" (N-FSMs). This is achieved through explicit layerwise constructions that encode DFA state transitions in the network’s depth, enabling precise realization of regular languages and delineating a formal expressivity boundary for such networks. The central results formalize layer and parameter requirements, provide state compression strategies, establish embeddings of Myhill–Nerode equivalence classes into continuous latent spaces, and rigorously show that fixed-depth networks cannot recognize non-regular languages (Dhayalkar, 16 May 2025).

1. Definition and Theoretical Framework

A deterministic finite automaton is defined as a 5-tuple M=(Q,Σ,δ,q0,F)M = (Q, \Sigma, \delta, q_0, F), where QQ is a finite set of nn states, Σ\Sigma a finite input alphabet of size kk, δ:Q×Σ→Q\delta: Q \times \Sigma \to Q the deterministic transition function, q0∈Qq_0 \in Q the initial state, and F⊆QF \subseteq Q the accepting states. On input x=s1s2⋯sT∈ΣTx = s_1 s_2 \cdots s_T \in \Sigma^T, the DFA recursively applies ht=δ(ht−1,st)h_t = \delta(h_{t-1}, s_t) for QQ0 and accepts if QQ1.

An N-FSM corresponding to QQ2 is a feedforward network QQ3 satisfying QQ4 if QQ5 and QQ6 otherwise. At each network layer, the hidden representation encodes the DFA state and the final layer tests for membership in QQ7 (Dhayalkar, 16 May 2025).

2. Explicit Construction of Feedforward Emulators

Given a DFA QQ8, the emulation proceeds through explicit neural architectures:

2.1. One-Hot Encodings

  • Symbols: Each QQ9 is represented by nn0.
  • States: Each nn1 is mapped to nn2.
  • At step nn3, the hidden state nn4 is concatenated with nn5 to form the input to the transition module.

2.2. Two-Layer Transition Modules

  • Hidden Layer: For each nn6, an “AND-unit” nn7 ensures activation if and only if the network is in state nn8 and receives symbol nn9.
  • Output Layer: The next state Σ\Sigma0 is computed as a sum over the activated Σ\Sigma1, with weights Σ\Sigma2 iff Σ\Sigma3.

2.3. Readout Layer

Once Σ\Sigma4 symbols are processed, the network produces Σ\Sigma5. The indicator Σ\Sigma6 (with Σ\Sigma7 iff Σ\Sigma8) determines acceptance.

2.4. Depth and Width Bounds

Construction Depth Σ\Sigma9 Width kk0
One-hot + ReLU kk1 kk2
Binary + threshold kk3 kk4

The construction ensures exact simulation for all kk5 of length kk6. For inputs restricted to at most kk7 symbols, kk8.

3. Exponential State Compression

State encodings can be exponentially compressed by representing DFA states as kk9-bit binary codes:

  • Binary State Encoding: Map each δ:Q×Σ→Q\delta: Q \times \Sigma \to Q0 to δ:Q×Σ→Q\delta: Q \times \Sigma \to Q1 with δ:Q×Σ→Q\delta: Q \times \Sigma \to Q2.
  • Transition Realization: Each output bit δ:Q×Σ→Q\delta: Q \times \Sigma \to Q3 is a Boolean function δ:Q×Σ→Q\delta: Q \times \Sigma \to Q4 specifying the δ:Q×Σ→Q\delta: Q \times \Sigma \to Q5-th bit of δ:Q×Σ→Q\delta: Q \times \Sigma \to Q6.
  • Threshold Circuits: Classical results guarantee a depth-2 threshold circuit for any finite Boolean function. Each bit is realized via threshold gates.

This approach achieves hidden-state width δ:Q×Σ→Q\delta: Q \times \Sigma \to Q7. Depth and overall layer width are preserved at δ:Q×Σ→Q\delta: Q \times \Sigma \to Q8 and δ:Q×Σ→Q\delta: Q \times \Sigma \to Q9, respectively (Dhayalkar, 16 May 2025).

4. Myhill–Nerode Equivalence and Latent Embeddings

The Myhill–Nerode relation partitions strings into equivalence classes corresponding to DFA states:

  • Embedding Theorem: There exists a feedforward network q0∈Qq_0 \in Q0 such that q0∈Qq_0 \in Q1 iff q0∈Qq_0 \in Q2. If q0∈Qq_0 \in Q3, then q0∈Qq_0 \in Q4.
  • Construction: Run DFA simulation to obtain q0∈Qq_0 \in Q5, then project using q0∈Qq_0 \in Q6 mapping each q0∈Qq_0 \in Q7 to distinct q0∈Qq_0 \in Q8 in q0∈Qq_0 \in Q9.
  • Johnson–Lindenstrauss Compression: The set F⊆QF \subseteq Q0 can be further reduced to dimension F⊆QF \subseteq Q1 while preserving linear separability, thus embedding equivalence classes in low-dimensional latent space (Dhayalkar, 16 May 2025).

5. Expressivity Limitations: Boundary for Regular Languages

Feedforward networks of fixed depth and width possess a finite partitioning capacity:

  • Linear Region Bound: For depth F⊆QF \subseteq Q2 and width F⊆QF \subseteq Q3, any such network partitions input space F⊆QF \subseteq Q4 into F⊆QF \subseteq Q5 regions.
  • Non-Regular Language Limitation: Languages such as F⊆QF \subseteq Q6 require capacity for infinitely many regions, which exceeds what is possible for fixed F⊆QF \subseteq Q7 and F⊆QF \subseteq Q8. Thus, such networks cannot recognize non-regular languages.
  • Formal Lower Bound: For every such network, there exists F⊆QF \subseteq Q9 such that, for all x=s1s2⋯sT∈ΣTx = s_1 s_2 \cdots s_T \in \Sigma^T0, correct classification of all strings in x=s1s2⋯sT∈ΣTx = s_1 s_2 \cdots s_T \in \Sigma^T1 is impossible. Only regular languages are exactly recognizable (Dhayalkar, 16 May 2025).

6. Synthesis of Results and Architectural Trade-Offs

Emulation Mode Depth x=s1s2⋯sT∈ΣTx = s_1 s_2 \cdots s_T \in \Sigma^T2 Width x=s1s2⋯sT∈ΣTx = s_1 s_2 \cdots s_T \in \Sigma^T3 State Width
One-hot encoding + ReLU x=s1s2⋯sT∈ΣTx = s_1 s_2 \cdots s_T \in \Sigma^T4 x=s1s2⋯sT∈ΣTx = s_1 s_2 \cdots s_T \in \Sigma^T5 x=s1s2⋯sT∈ΣTx = s_1 s_2 \cdots s_T \in \Sigma^T6
Binary encoding + threshold x=s1s2⋯sT∈ΣTx = s_1 s_2 \cdots s_T \in \Sigma^T7 x=s1s2⋯sT∈ΣTx = s_1 s_2 \cdots s_T \in \Sigma^T8 x=s1s2⋯sT∈ΣTx = s_1 s_2 \cdots s_T \in \Sigma^T9
Myhill–Nerode embedding ht=δ(ht−1,st)h_t = \delta(h_{t-1}, s_t)0 ht=δ(ht−1,st)h_t = \delta(h_{t-1}, s_t)1 ht=δ(ht−1,st)h_t = \delta(h_{t-1}, s_t)2
  • State Compression: Exponential compression from ht=δ(ht−1,st)h_t = \delta(h_{t-1}, s_t)3-dim. one-hot to ht=δ(ht−1,st)h_t = \delta(h_{t-1}, s_t)4-bit binary without sacrificing expressivity for finite-state computations.
  • Latent Embeddings: Faithful, linearly-separable vectorial mapping of equivalence classes, with further dimension reduction via random projection possible.
  • Expressivity Boundary: The constructive approach delineates that regular languages are both the upper and lower bounds of what N-FSMs can recognize with fixed architecture.
  • Bridging Symbolic and Neural Computation: These results rigorously instantiate a blueprint for realizing symbolic algorithms within neural architectures (Dhayalkar, 16 May 2025).

7. Context and Significance

The established equivalence between neural finite-state machines and DFAs provides a mathematically precise characterization of neural network capacity in symbolic sequence processing, automata simulation, and neural-symbolic integration. The constructive nature of the methods contrasts with prior heuristic or probing-based analyses, supplying explicit network weights, architectures, and representations. This formalization enables principled design of neural models for tasks where regular language structure is fundamental, while also identifying exact limits for problems involving unbounded memory or non-regular languages. As such, universal FSA emulation serves as a foundational result, bridging disciplines and informing further research on the correspondence between discrete automata and continuous neural computation (Dhayalkar, 16 May 2025).

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