Unified Paging in Modern Systems

Updated 20 October 2025

Unified paging is a mechanism that unifies page management across diverse memory and storage systems, offering programmability, performance, and scalability in complex environments.
It integrates multi-pager kernel designs, advanced heuristics for NP-hard caching problems, and hierarchical algorithms to significantly improve hit/miss ratios and reduce overhead.
In specialized contexts such as GPU acceleration and deep learning, unified paging adapts to dynamic workload demands to optimize latency, throughput, and resource utilization.

Unified paging refers to a class of mechanisms, abstractions, and algorithms that enable efficient, flexible, and consistent paging across heterogeneous resources, memory levels, or service providers in modern computing environments. Unified paging can mean intra-kernel per-region pagers in microkernels, user-driven page management abstractions over diverse storage hierarchies, hybrid object/page-accessed data planes, or GPU-accelerated, device-initiated paging—all with the objective of providing programmability, performance, and scalability in environments where memory and storage are fragmented, complex, and dynamic.

1. Unified Paging in Operating Systems and Microkernels

Unified paging in the context of operating systems, especially second generation microkernels, addresses the challenge of enabling efficient support for processes serviced by multiple pagers, each responsible for different parts of the address space. Traditional microkernels, such as L4, assigned a single pager per task, necessitating runtime-level indirection or region mapping to support multi-pager environments.

The enhanced multi-pager mechanism embeds region-based multi-pager support directly into the kernel. The approach (Klimiankou, 2014) partitions the user space into fixed-size regions, each managed by an individual pager, with a kernel-maintained regions table mapping region indices to pager thread IDs. For a virtual address $A_v$ :

$RID = \frac{A_v - B_{us}}{RS}$

where $B_{us}$ is the base of user space and $RS$ the region size (a power of two, permitting efficient bit-shift computation). When a page fault occurs, the kernel computes the region index, looks up the responsible pager, and dispatches the page fault directly, eliminating additional thread and mode switches.

Architecture	Mode Switches	Context Switches
Monolithic Kernel	2	0
Proposed Approach	4	2
L4+L4Re (Fiasco)	6	3

This arrangement achieves a one-third reduction in overhead compared to L4+L4Re (Fiasco.OC), introduces just one 4KB per-address-space regions table, and supports concurrent servicing by multiple paging servers, directly enhancing flexibility for applications managing stacks, memory-mapped files, and shared segments.

2. Unified Paging and Algorithmic Generality

Unified paging in the theoretical sense concerns the development of algorithms and policies for generalized paging/caching problems. The classic paging model is polynomially solvable for unit-size, uniform-cost pages using Belady’s algorithm. However, as soon as even small diversity in page size or cost is introduced, the offline variant becomes strongly NP-hard—even when all page sizes are restricted to $\{1,2,3\}$ (Folwarczný et al., 2015). This result holds both in the fault model (all faults have cost 1) and the bit model (cost is proportional to size).

This hardness precludes efficient offline unified paging strategies in the general case, necessitating heuristics and approximation schemes (no PTAS is known; the best-known approximation is a 4-approximation), and rendering online algorithms crucial for practical systems. The research also suggests the need to identify and exploit special cases with tractable structure to make unified paging feasible in real systems.

3. Hierarchical and Multi-level Memory Unified Paging

Emerging system architectures, incorporating multiple tiers of main memory (DRAM, SCM, NVM, etc.), require unified paging schemes transcending the classic two-level hierarchy. The N-level adaptation of the Aging algorithm (Oren, 2017) offers a paradigm where the eviction target for a page is determined by the leading zero count of its age counter, mapping pages to memory levels based on recency-of-use:

$L = \left \lceil \frac{Z}{Z_{\text{total}}} \times ML \right \rceil$

with $Z$ the number of leading zeros, $Z_{\text{total}}$ the counter width, and $ML$ the number of memory levels. Simulations demonstrate that such N-level hierarchical algorithms can provide significantly higher hit/miss ratios—up to $N$ times better—for workloads with large active page sets and relatively small main memory footprints, especially in HPC and memory-scarce environments.

4. Unified Paging in Heterogeneous and Application-Driven Contexts

Unified paging mechanisms now extend to user-space, enabling fine-grained application-driven control over paging parameters and the mapping of data across diverse storage/media. UMap (Peng et al., 2019) exemplifies a user-space unified paging framework that decouples page management from kernel-centric, one-size-fits-all services (like mmap), supporting custom page sizes, prefetching, and explicit eviction policies, all via extensible abstractions over various storage backends.

This shift allows dynamic adaptation to workload access patterns and storage characteristics, increasing hit rates and throughput by up to $2.5\times$ in benchmarks. Key technical ingredients include the use of Linux userfaultfd to capture and resolve page faults in user space, a backend object abstraction layer for extensibility, and multi-group thread pools for I/O decoupling and dynamic load balancing.

5. Hybrid and Adaptive Data Planes for Far Memory

For far-memory and remote memory scenarios, unified paging must concurrently support page-granular and fine-grained object-granular access paths. Atlas (Chen et al., 23 Jun 2024) provides a runtime–kernel co-design where each page is dynamically assigned an access path based on always-on profiling of spatial locality using Card Access Tables (CATs). The card access rate (CAR):

$CAR = \frac{\sum_{i=1}^N CAT[i]}{N} \times 100\%$

guides the hybrid policy: pages with high CAR are accessed via kernel paging (amortizing network and disk I/O), while low-CAR pages are accessed via object fetching. Atlas demonstrates throughput gains (1.5–3.2 $\times$ over AIFM/FastSwap) and tail latency reduction (1–2 orders of magnitude) by dynamically transitioning pages between paging and object-fetching modes as locality shifts.

6. Unified Paging for Accelerators and Deep Learning Systems

The exponential increase in data-intensive accelerator workloads exposes the limitations of OS-and-CPU-centric unified virtual memory (UVM) approaches. GPUVM (Nazaraliyev et al., 8 Nov 2024) forgoes OS-managed page faults, equipping the GPU with direct control of page management and RDMA-based on-demand paging. GPU threads detect missing pages, coordinate via leader-election, and post RDMA fetch requests (using a NIC mapped into GPU space) directly, bypassing the CPU and OS.

Key design parameters—such as the optimal outstanding request count for bandwidth saturation—are determined via Little’s Law; GPUVM achieves up to $4\times$ higher performance than UVM for latency-bound workloads, reduces page fault latency, and better manages oversubscription via fine-grained paging and parallelism.

In deep learning training on constrained hardware, POET (Patil et al., 2022) addresses unified paging by formulating a mixed-integer linear program that co-optimizes when to rematerialize activations versus paging them to auxiliary (flash) storage. Unlike naive rematerialization or paging, the unified model weighs per-activation energy and memory costs in a single optimization framework, meeting strict memory budgets and real-time deadlines for on-device training within as little as 32KB RAM.

7. Scalability and Heterogeneity: Online Unified Paging Models

Unified paging models are further generalized by the paper of slot-heterogeneous paging (Chrobak et al., 2022), where each request specifies a set of permissible cache slots. Competitive ratio analysis reveals exponential costs in the worst-case but identifies tractable subclasses (e.g., laminar slot families) with bounded ratios, extending the theoretical underpinnings of unified paging across cache architectures with specialized slot/topology constraints.

The statistical analysis of modern cloud workloads (Mari et al., 11 Jan 2024) reveals that page request distributions often follow a multi-core power law, resulting in “flattened” request frequency tails best modeled by Pareto type II (Lomax) distributions. Theoretical results show that classic online policies (e.g., LRU, LFU) maintain $O(1)$ performance on such distributions—not just adversarially but in the stochastic “typical-case”—explaining the success of unified, simple eviction strategies in multi-core, multi-VM cloud environments.

Unified paging encompasses an evolving spectrum of architectural, algorithmic, and systems-level solutions, all designed to manage memory and storage in a manner that is both performance-optimal and sensitive to the diversity and heterogeneity of emerging hardware and software environments. Continued research highlights not only the algorithmic hardness inherent to general paging/caching but also the practical routes—embedding paging in kernels, exposing user-driven abstractions, adapting online, and leveraging co-design—that enable scalable, maintainable, and efficient unified paging across the computational stack.