Unified Memory Architecture

Updated 27 May 2026

Unified Memory Architecture is an integrated memory model that provides a single, cache-coherent address space for CPUs, GPUs, and accelerators.
UMA simplifies programming by removing the explicit software-managed data transfers, thus reducing memory footprint and streamlining application development.
UMA enhances performance by enabling high-speed data access and lowering migration overhead, achieving up to 5× speedup over traditional discrete memory approaches.

Unified Memory Architecture (UMA) refers to an architectural design in which multiple high-performance compute agents—such as CPUs and hardware accelerators (e.g., GPUs, NPUs, or PIM subsystems)—share a single, hardware-coherent physical memory space. UMA removes the conventional boundary between “host” and “device” memory, enabling all system agents to issue loads and stores into a unified, cache-coherent address space, thereby eliminating explicit software-managed data transfers. The paradigm facilitates simplified programming, lower memory footprint, and higher performance and scalability across diverse high-performance, AI, and data-centric workloads (Tandon et al., 2024, Wahlgren et al., 18 Aug 2025, Aananthakrishnan et al., 2020, Li, 2024, Seo et al., 2024, Pratipat, 9 May 2026, Zhang et al., 2023, Zhou et al., 11 Jan 2026).

1. Hardware Architecture and System Models

At its core, UMA is realized either by physical integration of compute elements with shared DRAM pools or by cache-coherent interconnects bridging multiple memory domains. The AMD Instinct MI300A APU exemplifies the former by packaging Zen 4 EPYC CPU cores and fourth-generation CDNA GPU dies alongside a single 128 GiB HBM3 pool, all interconnected with a unified I/O fabric and accessed over a flat 64-bit address space. In this design, all memory requests—whether originating from CPU or GPU—map to the same physical DRAM region, with hardware-level coherence ensuring immediate data visibility across all agents (Tandon et al., 2024, Wahlgren et al., 18 Aug 2025).

A similar coherence and address-space model persists in the NVIDIA Grace-Hopper “superchip,” where an Arm Grace CPU and NVIDIA H100 GPU share separate physical LPDDR5X and HBM3e pools interconnected via bidirectional cache-coherent NVLink Chip-to-Chip (C2C), presenting both memory types as NUMA domains within a single virtual space. Accesses through NVLink are cache-coherent and respect home-node MESI-style protocols, eliminating the need for manual data copies or CUDA/HIP memory management APIs (Li, 2024, Li et al., 2024).

Other exemplars include Apple M4 Pro UMA (CPU and GPU integrated on-package with shared LPDDR5X DRAM), PIUMA (Programmable Integrated Unified Memory Architecture with Distributed Global Address Space/DGAS across nodes, offering 8 B fine-grained accesses and full-address-space visibility) (Aananthakrishnan et al., 2020), G10 (GPU-Host-SSD UVM address space with hardware-managed page-table integration) (Zhang et al., 2023), IANUS (NPU and PIM sharing GDDR6 in a single physical memory with coordinated DMA and in-place computation) (Seo et al., 2024), and software/AI system-level frameworks such as MemTrust, in which unified memory refers to logically integrated and cryptographically protected context memory for distributed AI agents (Zhou et al., 11 Jan 2026).

2. Key Mechanisms: Addressing, Coherence, and Memory Management

UMA mandates mechanisms for:

Flat (or hierarchically NUMA) virtual address spaces: All system agents use the same 64-bit (or wider) pointer representation to address shared memory. Allocation policies (e.g., first-touch, device-first-use, block interleaving) determine physical placement within or across domains (Li, 2024, Aananthakrishnan et al., 2020).
Hardware-level cache coherence: MESI or MOESI protocols maintain validity and consistency across CPU, GPU, and other agent caches. NVLink C2C, Infinity Fabric, and similar fabrics propagate coherency events for cross-domain updates (Wahlgren et al., 18 Aug 2025, Tandon et al., 2024).
Coherence overhead and cross-domain contention: Under heavy CPU-GPU contention, throughput reduction on the “weaker” agent (typically CPU) can reach up to 89%, as observed in atomic histograms on MI300A (Wahlgren et al., 18 Aug 2025). On-chip memory (e.g., Infinity Cache) may opt out of coherence to avoid snoop-related latency and bandwidth collapse.
Allocation and page migration strategies: UMA systems distinguish between up-front (e.g., hipMalloc) and on-demand (malloc, Managed) allocation, which affects TLB fragmentation, page-fault latency, and effective bandwidth. Optimal performance requires up-front allocation and, where possible, first-touch initialization on the agent (CPU or GPU) that will initially access the data (Wahlgren et al., 18 Aug 2025, Li, 2024, Li et al., 2024).
Page-fault handling: Unified page tables synchronize physical-to-virtual mappings between CPU and accelerator. Hardware replay mechanisms (e.g., XNACK on MI300A) and Linux HMM ensure efficient resolution, with minor faults achieving latency as low as 9–18 µs (Wahlgren et al., 18 Aug 2025).

3. Programming Paradigms and Abstractions

UMA magnifies programming productivity by abstracting away explicit data movement. Key paradigms include:

OpenMP 5.x unified_shared_memory: A single compiler directive (#pragma omp requires unified_shared_memory) ensures all allocations reside in the unified pool. Offloading, host–device interoperability, and synchronization are managed implicitly, with no need for explicit map/to/from clauses or vendor-specific APIs (Tandon et al., 2024).
Device First-Use Data Movement: In Grace-Hopper, pages physically migrate to the agent (“device”) that first touches them. SCILIB-Accel implements a “Device First-Use” wrapper to ensure pages migrate only once (e.g., to HBM3e for GPU BLAS), amortizing the transfer overhead across hundreds of uses (Li, 2024).
Automatic/transparent offload frameworks: Tools intercept library calls (e.g., BLAS dgemm) at the binary level, triggering offload, data migration, and memory placement decisions automatically, with minimal or no user code modification (Li, 2024, Li et al., 2024).
Distributed Global Address Space (PIUMA): Pointers are global; fine-grained DMA, gather/scatter, remote atomics, and software-managed caching/scratchpads enable latency hiding and scalability for large-scale graph and irregular workloads (Aananthakrishnan et al., 2020).
Hierarchical AI memory systems: Logical unification of storage, retrieval, and learning (e.g., MemTrust) overlays hardware memory unification with cross-application, policy-governed context exposure, always with cryptographic isolation and remote attestation (Zhou et al., 11 Jan 2026).

4. Performance Characterization and Comparative Analysis

UMA’s main performance gains derive from:

Elimination of explicit host↔device data transfers: Benchmarks on MI300A (OpenFOAM CFD) demonstrate 60–70% of runtime on discrete GPUs is due to page migrations and buffer copies—eliminated in UMA, yielding 4–5× speedup over H100/A100 and 5× over MI210. Memory footprint is reduced to a single copy, matching CPU-only code (Tandon et al., 2024).
Full-bandwidth access: In MI300A, GPU with hipMalloc achieves 3.6 TB/s (≈67% of HBM3 peak), while discrete PCIe GPUs are limited to < 1 TB/s interconnect (Wahlgren et al., 18 Aug 2025). On Grace-Hopper, cross-domain NVLink achieves ≈450 GB/s bidirectional, a 10× improvement over PCIe-based discrete systems (Li, 2024, Li et al., 2024).
High-usage amortization: When reused across many kernels, the initial migration cost is amortized—for example, MuST’s LSMS method attains a 3× speedup using Device First-Use, as each large matrix is reused >700 times (Li, 2024).
Fine-grained, latency-hiding granularity: PIUMA’s 8 B access granularity, hardware DMA, and unified network yield up to 279× speedup in random-walk, 111× in SpMSpV, and near-linear scaling across 16 nodes (Aananthakrishnan et al., 2020).

System	Bandwidth (GB/s)	Memory Overhead Eliminated	Speedup vs. Discrete
AMD MI300A	3,600 (GPU), 208 (CPU)	Yes	4–5× (H100)
Grace-Hopper NVL	3,400 (GPU), 318 (CPU)	Yes	2–3× (PARSEC BLAS)
Apple M4 Pro	224 (CPU & GPU)	Yes	3–10× (quantum sim)
PIUMA	1–6 TB/s (net)	Yes	10–300×+ (1–16 nodes)

UMA may introduce new sources of contention (e.g., cross-domain atomic operations) and requires careful allocator/placement decisions for optimal TLB/DRAM interleaving (Wahlgren et al., 18 Aug 2025).

5. Application Domains and Case Studies

Scientific Computing (HPC): Large production codes such as OpenFOAM can be offloaded incrementally on MI300A via OpenMP with unified memory, enabling million-line-scale code acceleration without large rewrites (Tandon et al., 2024).
Numerical Linear Algebra/Batched BLAS: Quantum chemistry/physics codes (MuST, PARSEC) see up to 3× speedup on Grace-Hopper with zero code change via SCILIB-Accel and first-use placement (Li, 2024, Li et al., 2024).
AI Workloads: IANUS leverages in-memory PIM and NPU unification to accelerate transformer inference (GPT-2) by 6.2× over NVIDIA A100 by maximizing memory bandwidth utilization while removing staging bottlenecks (Seo et al., 2024).
Deep Learning: G10 achieves 1.75× throughput (BERT, ViT) over prior solutions by integrating HBM, host DRAM, and SSD into a single address space, using DNN compiler analysis for pre-emptive smart tensor migration (Zhang et al., 2023).
Contextual AI Memory: MemTrust extends the UMA principle to data governance and cross-application context, with strict cryptographic guarantees for data/metadata fusion (Zhou et al., 11 Jan 2026).
Graph Analytics: PIUMA achieves up to 29× (SpMV) to 279× (random walks) speedup over Xeon and linear scale-out to several thousand nodes for sparse and irregular workloads (Aananthakrishnan et al., 2020).

6. Scalability, Limitations, and Future Directions

UMA’s systemic scalability is determined by both hardware design and software stack support:

Scale-out: PIUMA’s DGAS and HyperX+optical fabric delivers 100–150 ns end-to-end latency for 8 B RDMA up to thousands of nodes; G10’s scheduling extends naturally to multi-GPU and RAID-shared SSD (Aananthakrishnan et al., 2020, Zhang et al., 2023).
Workload regularity dependency: G10’s static tensor lifetime modeling excels for static/iterative DNN, but less effective for irregular graph or dynamic dataflow—requiring online adaptation or fallback (Zhang et al., 2023).
Contention and coherence: High cross-domain contention can degrade CPU throughput sharply; bypass strategies (e.g., using non-coherent caches, command scheduling in IANUS) are necessary (Wahlgren et al., 18 Aug 2025, Seo et al., 2024).
Allocator and page-size dependencies: Performance is sensitive to allocation policy (e.g., contiguous hipMalloc, page-aligned HBM allocations) and system page size (64 KB preferred for CUDA) (Wahlgren et al., 18 Aug 2025, Li, 2024).
Security and trust: Logical UMA for AI memory (e.g., MemTrust) contends with both hardware-level privacy and cross-application context sharing, requiring extensive TEE and attestation mechanisms for data sovereignty (Zhou et al., 11 Jan 2026).

Unified memory architecture continues to generalize across HPC, AI, and cloud contexts, with emerging directions including comprehensive support for persistent and disaggregated memory (CXL-attached), dynamic workload-aware allocation, AI-powered memory scheduling, and full-lifecycle cryptographic data governance.

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