Unified INT32/FP32 Cores

• Unified INT32/FP32 cores are advanced architectures that execute both 32-bit integer and floating-point operations through a shared datapath, enhancing mixed-precision efficiency.
• Innovative features such as dynamic fixed-point representation, flexible instruction sets, and dual FMA pipelines maintain balanced throughput and mitigate overflow risks.
• Empirical results demonstrate significant performance boosts in CNN training and general-purpose tasks, optimizing resource usage while sustaining state-of-the-art accuracy.

Unified INT32/FP32 cores implement both 32-bit floating-point (FP32) and 32-bit integer (INT32) operations through a shared processing datapath. Such designs facilitate mixed-precision computation—essential for efficient neural network training and high-throughput general-purpose (GP) computing—by supporting time-multiplexed execution of integer and floating-point arithmetic with minimal hardware overhead. Core innovations include dynamic fixed-point representation with shared exponents, high-throughput FMA pipelines, overflow-mitigation strategies, unified register files, and flexible instruction-set architectures. These advancements, realized in both GP CPU designs and reconfigurable soft-GPGPU architectures, enable state-of-the-art accuracy and performance on large-scale workloads while optimizing resource utilization.

1. Shared-Exponent Dynamic Fixed-Point Representation

Dynamic Fixed Point (DFP) schemes encode tensors as arrays of $P$-bit signed integers ($I = \{i_0, i_1, \ldots\}$) and a single shared exponent ($E_s$), denoted DFP-$P \equiv \langle I, E_s \rangle$. Each floating-point value $f_n$ is reconstructed as $f_n = i_n \cdot 2^{E_s}$. Conversion from FP32 to DFP-$P$ entails:

1. Determining the exponent of the largest-magnitude entry: $E_{fmax} = E\bigl(\max_{f \in F} |f| \bigr)$, with $E(x) = \lfloor \log_2 |x| \rfloor$.
2. Choosing $E_s$ so $I = \{i_0, i_1, \ldots\}$0-bit integers fit: $I = \{i_0, i_1, \ldots\}$1.
3. Quantizing each value: $I = \{i_0, i_1, \ldots\}$2.

Upon conversion back, $I = \{i_0, i_1, \ldots\}$3. DFP enables uniform scaling and collective quantization across blocks of data, facilitating efficient integer arithmetic and data movement (Das et al., 2018).

2. Integer and Floating-Point FMA Pipelines

Unified core pipelines instantiate both INT16$I = \{i_0, i_1, \ldots\}$4INT16$I = \{i_0, i_1, \ldots\}$5INT32 and FP32 FMA mechanisms. For INT arithmetic, modern x86 cores (e.g., AVX512_4VNNI) perform parallel 16$I = \{i_0, i_1, \ldots\}$616-bit multiplications, accumulating into 32-bit registers. FP operations employ FP32 multipliers and adders. In integrated soft-GPGPU (eGPU) architectures, each Scalar Processor (SP) features:

• FP32 path: a DSP Block in “FP32-MAD” mode for multiply-accumulate.
• INT32 path: ALMs for logical/arithmetic ops and half-DSP for INT32 multiplication.

A TYPE field in instruction words steers pipeline dataflows, allowing each stage to selectively process FP32 or INT32 without duplicating hardware. Matching pipeline depths (e.g., 9 stages per path in eGPU) maintains balanced timing and hazard management (Langhammer et al., 2023).

3. Overflow Management in Mixed Precision Accumulation

32-bit accumulators risk overflow with large product chains. Two principal mitigation strategies exist:

• Input Shifting: Both INT16 operands are right-shifted by 1 bit, reducing product width to 29 bits and extending headroom.
• Periodic Output Flushing: After $I = \{i_0, i_1, \ldots\}$7 FMA operations ($I = \{i_0, i_1, \ldots\}$8–$I = \{i_0, i_1, \ldots\}$9), the INT32 accumulator is converted to FP32, rescaled by $E_s$0, then added to the output. This ensures no overflow at minimal instruction overhead ($E_s$11–3%).

This process is implementable by microarchitectural scheduling—interleaving integer FMAs and periodic INT$E_s$2FP conversions—for robust accumulation without performance loss (Das et al., 2018).

4. Practical Performance and Resource Utilization

Unified INT32/FP32 cores have demonstrated state-of-the-art results on convolutional neural network training and general-purpose compute kernels. Empirical results include:

• CNN Training: INT16$E_s$3INT32 mixed-precision, DFP-16, without hyperparameter modification, matches or surpasses FP32 accuracy (ResNet-50: 75.77% top-1 vs. 75.70% FP32; identical throughput iterations) on ImageNet-1K (Das et al., 2018).
• Throughput: Mixed-precision training on 32 XeonPhi nodes yields a 1.8$E_s$4 throughput boost (154 img/s FP32 $E_s$5 276–317 img/s INT16/INT32).
• eGPU Scalar Multiprocessor: Single SM yields 24.67 GFLOP/s (FP32) and 12.34 GIOP/s (INT32) at 771 MHz, with measured kernel efficiencies (FFT $E_s$625%, QRD $E_s$722%) bottlenecked primarily by memory bandwidth (Langhammer et al., 2023).

Architecture	FP32 Throughput	INT32 Throughput	Peak Frequency
XeonPhi (INT16/INT32 FMA)	–	1.8× vs. FP32	–
eGPU (single SM)	24.67 GFLOP/s	12.34 GIOP/s	771 MHz

5. Unified Core Microarchitectural Features

Essential building blocks for unified INT32/FP32 cores include:

• Wide vector datapaths (≥512 bits) shared between FP and INT pipelines.
• INT16 multipliers, INT32 accumulators, FP32 multipliers/adders, and respective register files.
• Programmable barrel shifters on INT inputs for precision/headroom control.
• Exponent management modules: leading-zero counters, max-exponent computation, broadcast logic.
• Fast conversion units (INT32→FP32) and scaling multipliers for rescaling partial sums.
• Multi-phase schedules for register file access and memory.
• Flexible ISAs supporting instruction-level selection of FP/INT operation types and variable wavefront/block sizes.

These features enable high resource utilization, minimize timing bottlenecks (FP32–MAD chain in DSP Blocks), and maintain scalability—four SMs per Agilex FPGA sector, with $E_s$8 frequency loss at packing boundaries (Langhammer et al., 2023).

6. Scalability and Practical Deployment

Unified INT32/FP32 designs—both hardwired and soft (FPGA)—scale efficiently across device sectors. eGPU implementations show linear performance scaling up to four SMs per sector; subsequent scaling is limited by interconnect delays and routing penalties, with device-level ALM:DSP:M20K ratios maintained for uniform efficiency. Physical clustering of DSP Blocks and memory banks close to SP arrays minimizes latency.

A plausible implication is that further integration of such unified pipelines into general-purpose cores (CPU, GPGPU) will streamline mixed-precision algorithm deployment, reduce memory and compute overheads, and facilitate future research into multi-modal, resource-balanced architectures.

7. Implications and Prospects

Unified INT32/FP32 cores, as demonstrated in (Das et al., 2018) and (Langhammer et al., 2023), facilitate mixed-precision algorithm deployment with robust accuracy guarantees and substantial computational throughput improvements. Architectures utilizing time-shared DSP hardware and carefully balanced pipeline depths raise performance density standards for soft-processors and silicon designs. Continued evolution is expected to extend these practices into high-frequency reconfigurable platforms and general-purpose CPUs, supporting broader domains such as complex wireless linear solvers and large-scale neural network training.

A plausible implication is that exponent management, flexible shifting, and shared memory scheduling will become standard microarchitectural patterns in future unified core designs, supporting dynamic precision scaling and efficient resource allocation.