Uncertainty-Tracking Processor Architectures

• Uncertainty-tracking processor architectures are a family of designs that explicitly represent and manipulate uncertainty across the hardware-software stack.
• They employ diverse methods such as explicit belief-state tracking, runtime delay estimation, and intentional uncertainty injection to optimize performance and power.
• These architectures integrate uncertainty management into both design-time analysis and runtime control, offering enhanced robustness and efficiency.

Searching arXiv for the supplied papers and closely related entries to ground the article in current metadata. import urllib.request, ssl, re, xml.etree.ElementTree as ET, textwrap, json, os, sys, math ids = ["(Yan et al., 2021)","(Denil et al., 2011)","(Hosseinzadeh et al., 2017)","(Phipps et al., 2015)","(Kempf et al., 2014)","(Diavastos et al., 2021)","(He et al., 2019)"] url = "http://export.arxiv.org/api/query?id_list=" + ",".join(ids) try: data = urllib.request.urlopen(url, timeout=20).read().decode("utf-8") print(data[:1000]) except Exception as e: print("ERR", e) result = urllib.request.urlopen(url, timeout=20).read().decode("utf-8")[:1000] analysis to=python code url = "http://export.arxiv.org/api/query?id_list=" + ",".join(ids) try: data = urllib.request.urlopen(url, timeout=20).read().decode("utf-8") print(data[:1500]) except Exception as e: print("ERR", repr(e)) analysis to=python code import urllib.request, socket socket.setdefaulttimeout(10) url = "http://export.arxiv.org/api/query?id_list=" + ",".join(ids) try: with urllib.request.urlopen(url) as r: data = r.read().decode("utf-8") print("LEN", len(data)) print(data[:800]) except Exception as e: print(type(e), e) analysis to=python code print("hello") analysis to=python code hello analysis to=python code Uncertainty-tracking processor architectures are architectures in which uncertainty is treated as an internal systems object rather than an external nuisance. In the literature, that object appears in several distinct forms: an explicit posterior belief over hidden state in a perception-control loop, a runtime record of load-latency variation used for instruction scheduling, a software-visible mechanism for injecting controlled timing and power uncertainty, a pre-characterized statistical model of device error used for accelerator co-design, and a sample-propagation or surrogate-modeling layer for uncertainty quantification on conventional parallel machines. The field is therefore not organized around a single canonical microarchitecture, but around a family of mechanisms for representing, propagating, exploiting, or intentionally shaping uncertainty across the system stack (Denil et al., 2011, Hosseinzadeh et al., 2017, Diavastos et al., 2021, Yan et al., 2021, Phipps et al., 2015, Kempf et al., 2014, He et al., 2019).

1. Scope and architectural patterns

The literature suggests that “uncertainty-tracking” is best understood as an umbrella term spanning at least five recurrent architectural patterns. Some works maintain an explicit probabilistic state during execution; some memorize dynamic variability as a scalar predictor; some deliberately inject uncertainty into externally observable behavior; and others move uncertainty handling to compilation, neural architecture search, or design-space exploration. This breadth is important, because papers in the area often share vocabulary while differing sharply in whether uncertainty is estimated online, represented explicitly, or only pre-characterized offline.

Pattern	Representative mechanism	Representative papers
Explicit belief-state tracking	Particle-filter posterior drives sensing and control	(Denil et al., 2011)
Runtime variability tracking	Latest observed load delay predicts issue time	(Diavastos et al., 2021)
Controlled uncertainty generation	Cacheline on-off flags create intentional misses	(Hosseinzadeh et al., 2017)
Offline robustness-by-design	Statistical hardware-error model inside training and NAS	(Yan et al., 2021)
Software and design-time uncertainty propagation	Ensemble execution, timed-automata exploration, mixed-domain surrogate modeling	(Phipps et al., 2015, Kempf et al., 2014, He et al., 2019)

A central consequence is that architectural relevance does not require a dedicated uncertainty arithmetic unit or a probabilistic ISA. In some systems, uncertainty is the posterior $b_t = p(x_t \mid h_{1:t}, a_{1:t})$; in others, it is the learned load delay $T_{Delay}(p)$; in others, it is the configuration of cacheline metadata bits; and in others still, it is a distribution propagated through a simulator or solver stack. This suggests that the defining property is not hardware form factor but whether uncertainty is surfaced and used as a first-class design parameter.

2. Explicit probabilistic state and active control

A clear instance of explicit uncertainty-tracking appears in the attentional tracking-and-recognition architecture of (Denil et al., 2011). The system is organized as interacting identity and control pathways, intended to mirror “what” and “where” pathways. At time $t$, a gaze action $a_t$ selects a fixation point; the sensor returns a foveated observation; the identity pathway converts that observation into hidden features $h_t$ with RBM-based appearance modeling; and the control pathway updates the belief state with a Bayesian filter. The core recurrence is

$$b_t \propto p(h_t|x_t,a_t)\int p(x_t|x_{t-1},a_{t-1})\,p(dx_{t-1}|h_{1:t-1},a_{1:t-1}),$$

with nonlinear, non-Gaussian posteriors represented by particle filtering rather than by parametric moments (Denil et al., 2011).

This architecture is uncertainty-tracking in a strict computational sense because state is retained explicitly as a particle approximation to the posterior, not merely as recurrent activations. If there are $N$ particles, the posterior approximation is carried by the particle trajectories and weights, then updated through a predict-update-resample cycle. The control policy does not optimize over raw measurements; it optimizes over belief-dependent reward. The implemented uncertainty proxy is

$r_t = \sum_{i=1}^N (w_t^{(i)})^2,$

so the controller prefers fixations that sharpen the posterior by concentrating particle weights. In the partial-information setting, the paper then models the reward surface over continuous gaze locations with a Gaussian Process and selects actions with GP-UCB,

$$a_{t+1} = \arg\max_a m_t(a) + \sqrt{\beta_t}s_t(a),$$

making uncertainty appear twice: once in the tracker’s posterior over latent target state and once in the controller’s surrogate uncertainty over action utility (Denil et al., 2011).

The experimental results show why this decomposition matters. In full-information discrete-policy experiments, average tracking error was $2.5$ pixels for the learned policy versus $T_{Delay}(p)$0 for deterministic and $T_{Delay}(p)$1 for random, while average classification accuracy was $T_{Delay}(p)$2 versus $T_{Delay}(p)$3 and $T_{Delay}(p)$4. In the partial-information setting, Bayesian optimization achieved average tracking error $T_{Delay}(p)$5, whereas EXP3 reached $T_{Delay}(p)$6 with enormous variance. The paper is explicit, however, that this is not a processor microarchitecture paper: uncertainty is tracked algorithmically, not through ISA state or dedicated hardware. Its significance for processor-oriented research lies in the pattern it establishes—persistent belief memory, action-conditioned observation formation, posterior summarization, and uncertainty-guided control (Denil et al., 2011).

3. Runtime variability tracking and uncertainty injection in processor microarchitecture

The most direct microarchitectural example in the corpus is the issue-time-prediction processor with real-time load delay tracking (Diavastos et al., 2021). Its target is the energy and scalability cost of a reservation-station-based out-of-order scheduler. The paper argues that prior efficient schedulers fail mainly because predefined instruction latencies do not capture dynamic load latency. L2 accesses can vary by as many as 4 cycles, and DRAM accesses can vary by more than $T_{Delay}(p)$7 nominal cycle count. The architectural insight is that this variability is recurrent enough to track cheaply: on average, $T_{Delay}(p)$8 of repeated loads have the same access time in consecutive iterations across SPEC CPU2006. The proposed core therefore stores the latest observed issue-to-completion delay for L1-missing loads in a per-PC DelayCache and propagates those delays through producer-consumer chains:

$T_{Delay}(p)$9

$t$0

The main hardware structures are a 256-entry Dependency Table, a 512-entry direct-mapped DelayCache, and 5 per-functional-unit 13-entry priority queues. Using this mechanism, the processor reaches $t$1 of the performance of a traditional out-of-order processor while still consuming $t$2 less power; the proposed core uses $t$3 of OoO power and improves MIPS/Watt by $t$4 (Diavastos et al., 2021).

What this design tracks is not uncertainty in a probabilistic sense, but runtime latency variation encoded as a latest-value estimate. That distinction is fundamental. The processor does not maintain confidence intervals, multimodal latency states, or posterior distributions; it memorizes the most recent realized delay because more complex variants—storing multiple delays, using most frequent or average delay, or requiring repeated identical delays—did not improve performance materially. The resulting architecture is best described as a variability-tracking scheduler rather than a general uncertainty-quantification machine (Diavastos et al., 2021).

A different microarchitectural stance appears in Janus (Hosseinzadeh et al., 2017), which is not an estimator of uncertainty but a mechanism for creating it. Janus adds an on-off flag to each cache block. If tag match fails or the valid bit is not set, the access is an ordinary program miss. If tag and valid succeed but the on-off flag is off, the architecture forces an intentional miss. This changes the two-state hit/miss model into three outcomes—program miss, program hit with flag off, and program hit with flag on—and thereby randomizes timing and power observables for side-channel resistance. The cache exposes this mechanism via two ISA instructions, cache-block-on-i and cache-block-off-i, and the on-off check adds only “one single gate delay.” In a gate-level synthesized ARM-7 core, runtime variation was significant across benchmarks: under a random on-off scheme, mean execution time and variance were $t$5 ns and $t$6 for bubble sort, $t$7 ns and $t$8 for quick sort, and $t$9 ns and $a_t$0 for Fibonacci. Janus therefore represents a secure cache architecture that manages uncertainty through metadata and policy, but not one that measures or propagates uncertainty as a formal architectural quantity (Hosseinzadeh et al., 2017).

Taken together, these two papers delimit an important conceptual boundary. Real-time load-delay tracking uses live execution history to improve scheduling quality, whereas Janus intentionally perturbs externally visible behavior to blur timing and power signatures. Both manipulate uncertainty-related phenomena inside the processor, but only the former tracks a variable needed for forward execution decisions.

4. Emerging-device accelerators and offline robustness under hardware uncertainty

In emerging-device computing-in-memory accelerators, uncertainty often enters before execution begins, as a mismatch between trained weights and physically realized conductances. The CiM work in (Yan et al., 2021) studies an ISAAC-like crossbar-based DNN accelerator, assuming an RRAM implementation in which crossbar arrays store synaptic weights and perform analog matrix-vector multiplication in situ, while DACs and ADCs convert between digital activations and analog signals. The uncertainty model is intentionally aggregate:

$a_t$1

with $a_t$2 and a reported uncertainty level of $a_t$3. The deployed output for a fixed input becomes

$a_t$4

and the output perturbation is

$a_t$5

Across Monte Carlo trials, the paper reports that each coordinate of $a_t$6 is well approximated by a Gaussian; for one LeNet and one fixed MNIST image, 10,000 noise samples from $a_t$7 yielded $a_t$8 values below $a_t$9 and MSE values below $h_t$0 when fitting per-dimension output-change histograms (Yan et al., 2021).

The architectural contribution is not runtime uncertainty tracking in the strict microarchitectural sense. There is no online estimation hardware, no per-crossbar confidence metadata, no dynamic correction loop, and no runtime confidence propagation through inference. Instead, the paper uses a pre-characterized statistical model inside training, evaluation, and neural architecture search. The training procedure saves the clean weight tensor, injects one sampled perturbation, runs forward and backward propagation on the perturbed model, then restores the clean tensor and updates it with gradients computed under perturbation. The UAE framework then evaluates each candidate architecture under multiple Monte Carlo noise realizations and computes a reward either from mean accuracy or from a “95% minimum” robustness statistic. On CIFAR-10, this distributional objective changes conclusions sharply: QuantNAS found an architecture with $h_t$1 accuracy on ideal hardware, but its mean deployed accuracy under the uncertainty model collapsed to $h_t$2; NACIM achieved $h_t$3 mean noisy accuracy; UAE-M with $h_t$4 achieved $h_t$5 mean noisy accuracy and $h_t$6 95%-minimum accuracy; and UAE-95 with $h_t$7 achieved $h_t$8 on the 95%-minimum metric (Yan et al., 2021).

For uncertainty-tracking architecture research, the main lesson is architectural rather than circuit-level. The work shows that a processor or accelerator stack can benefit when a calibrated statistical error model of the storage-computation fabric is exposed to the optimizer rather than hidden beneath the implementation. At the same time, the paper is explicit about its limits: it does not model temporal drift, aging, retention loss, read disturb, spatial correlation, line resistance, IR drop, ADC nonlinearity, DAC quantization, or bit-sliced accumulation error, and it does not report area, energy, or throughput implications of the more robust networks it finds (Yan et al., 2021).

5. Software-supported uncertainty propagation and design-time architectural analysis

A large part of the literature moves uncertainty handling above the microarchitecture, treating conventional processors as substrates for fast uncertainty propagation rather than as objects that themselves maintain uncertainty metadata. Embedded ensemble propagation is the clearest example (Phipps et al., 2015). The method groups $h_t$9 samples into an ensemble, replaces the scalar type by an Ensemble<T,s> type, and propagates those samples simultaneously through the simulation. In the commuted Kronecker ordering, the outer sparse structure remains that of the original Jacobian, while each scalar nonzero becomes an $$b_t \propto p(h_t|x_t,a_t)\int p(x_t|x_{t-1},a_{t-1})\,p(dx_{t-1}|h_{1:t-1},a_{1:t-1}),$$0 diagonal block. This permits reuse of sparse graph data across samples, reduces memory bandwidth pressure, exposes a regular SIMD/SIMT dimension, and amortizes communication latency through one halo exchange per ensemble instead of one per sample. The approach was integrated into Trilinos through Stokhos, Kokkos, Tpetra, Belos, MueLu, Zoltan2, and Basker, and scaled to 131,072 cores on Titan. For a $$b_t \propto p(h_t|x_t,a_t)\int p(x_t|x_{t-1},a_{t-1})\,p(dx_{t-1}|h_{1:t-1},a_{1:t-1}),$$1 mesh with $$b_t \propto p(h_t|x_t,a_t)\int p(x_t|x_{t-1},a_{t-1})\,p(dx_{t-1}|h_{1:t-1},a_{1:t-1}),$$2, measured SpMV throughput rose from $$b_t \propto p(h_t|x_t,a_t)\int p(x_t|x_{t-1},a_{t-1})\,p(dx_{t-1}|h_{1:t-1},a_{1:t-1}),$$3 to $$b_t \propto p(h_t|x_t,a_t)\int p(x_t|x_{t-1},a_{t-1})\,p(dx_{t-1}|h_{1:t-1},a_{1:t-1}),$$4 GFLOP/s on Sandy Bridge, from $$b_t \propto p(h_t|x_t,a_t)\int p(x_t|x_{t-1},a_{t-1})\,p(dx_{t-1}|h_{1:t-1},a_{1:t-1}),$$5 to $$b_t \propto p(h_t|x_t,a_t)\int p(x_t|x_{t-1},a_{t-1})\,p(dx_{t-1}|h_{1:t-1},a_{1:t-1}),$$6 on an NVIDIA K20x, and from $$b_t \propto p(h_t|x_t,a_t)\int p(x_t|x_{t-1},a_{t-1})\,p(dx_{t-1}|h_{1:t-1},a_{1:t-1}),$$7 to $$b_t \propto p(h_t|x_t,a_t)\int p(x_t|x_{t-1},a_{t-1})\,p(dx_{t-1}|h_{1:t-1},a_{1:t-1}),$$8 on Xeon Phi. The paper is explicit that this is not a new hardware uncertainty-tracking processor; it is a software execution model that maps uncertainty propagation onto existing CPU, GPU, and accelerator architecture features (Phipps et al., 2015).

A complementary system-level view appears in the design-space exploration methodology of (Kempf et al., 2014). Here uncertainty is represented as bounded intervals for task work, bounded timing uncertainty or jitter for job arrivals, and deployment alternatives in mapping, scheduling, communication, and frequency selection. Applications and platforms are translated into timed automata; formal analysis uses the IF toolset with on-the-fly reachability and zones, while informal analysis uses Monte Carlo simulation with probabilistic interpretations of interval uncertainty. The framework supports periodic, periodic-with-jitter, periodic-with-uncertainty, bounded-variability, and bi-bounded-variability arrival models, and practical formal scalability is reported at roughly 20–25 clocks or concurrently active components. The resulting “tracking” occurs in the model semantics, not in hardware. Its significance is that uncertainty in workload arrivals, execution times, and deployment choices can change multicore conclusions about mapping, scheduling, and power-performance tradeoffs long before any concrete microarchitecture is fixed (Kempf et al., 2014).

Mixed generalized polynomial chaos extends this design-time perspective to mixed continuous-discrete architecture parameters (He et al., 2019). The surrogate model

$$b_t \propto p(h_t|x_t,a_t)\int p(x_t|x_{t-1},a_{t-1})\,p(dx_{t-1}|h_{1:t-1},a_{1:t-1}),$$9

is built from orthonormal basis functions defined for both continuous and integer-valued variables, then fitted using quadrature points chosen by a mixed-integer optimization. In the CMP case study, the paper reports that 95 carefully chosen samples achieve similar mean-estimation accuracy to $N$0 Monte Carlo samples. In a DRAM subsystem modeled with DRAMSim2, around 60–66 designed samples tracked bandwidth, power, latency, and DBUS utilization well, and the offline quadrature optimization took 12.5 minutes on a 3.4 GHz desktop while end-to-end time was roughly $N$1 lower than a 200-sample MC study. This is again not runtime uncertainty tracking, but it is highly relevant to architecture because many architectural variables—core counts, ECC strength, and DRAM timing parameters such as tRCD, tCL, tRP, and tWR—are inherently mixed-domain (He et al., 2019).

6. Conceptual boundaries, misconceptions, and research directions

A recurring misconception is that all “uncertainty-tracking” architectures maintain mathematically explicit uncertainty estimates during execution. The literature does not support that generalization. The gaze-control architecture tracks a posterior belief state explicitly; the issue-time-prediction processor tracks latest observed load delay; Janus creates and policy-manages uncertainty without measuring it; the CiM work pre-characterizes uncertainty offline and optimizes robustness against its distribution; and ensemble propagation, timed-automata exploration, and M-gPC treat uncertainty as a software or design-time object rather than as microarchitectural state (Denil et al., 2011, Diavastos et al., 2021, Hosseinzadeh et al., 2017, Yan et al., 2021, Phipps et al., 2015, Kempf et al., 2014, He et al., 2019).

Another misconception is that uncertainty-aware design is equivalent to worst-case guardbanding. Several of the papers argue against that view, albeit in different ways. The CiM NAS results show that clean-accuracy optimization can produce architectures that fail after deployment, while distributional evaluation over multiple perturbation samples yields materially more robust models. The scheduling work shows that a single latest-delay estimate can recover much of out-of-order performance when dynamic latency is repetitive, without maintaining a full probability model. The design-space exploration and M-gPC papers likewise show that interval or mixed-domain uncertainty can be propagated through abstract models or surrogates without collapsing everything to a pessimistic bound (Yan et al., 2021, Diavastos et al., 2021, Kempf et al., 2014, He et al., 2019).

The limitations identified across the papers are also revealing. The CiM model is static, i.i.d., and weight-centric; it lacks online uncertainty estimation, temporal drift, and peripheral analog nonidealities. The load-delay tracker stores only a latest-value point estimate and leaves coherence-induced variability and confidence-aware timing prediction to future work. Janus offers no runtime observability interface for the uncertainty it generates. The ensemble and timed-automata approaches depend on grouping assumptions, model abstractions, and scalability limits. M-gPC assumes mutually independent uncertain parameters and low-order polynomial approximability (Yan et al., 2021, Diavastos et al., 2021, Hosseinzadeh et al., 2017, Phipps et al., 2015, Kempf et al., 2014, He et al., 2019).

These limits suggest several converging directions. One plausible implication is that future uncertainty-tracking architectures will need tighter interfaces between hardware variability models and software optimization, such as per-array or per-layer uncertainty descriptors in analog accelerators, digital twins for in-the-loop noise emulation, or deployment-time recalibration when measured behavior departs from pre-characterized assumptions. Another is that runtime tracking may evolve from latest-value memorization toward confidence-aware timing prediction, multi-modal latency state, or phase/change detection. A third is that explicit probabilistic-state architectures may become more processor-oriented by accelerating particle filtering, posterior summarization, and uncertainty-guided control rather than leaving those entirely to software. The literature therefore points less toward a single uncertainty-tracking processor template than toward a spectrum of architectures in which uncertainty is surfaced, retained, and exploited at the level most appropriate to the workload and the source of variation (Yan et al., 2021, Diavastos et al., 2021, Denil et al., 2011).