Typman-KWS: Efficient Embedded Keyword Spotting

• Typman-KWS is a keyword spotting architecture that integrates MFCC feature extraction and a MobileNet-derived neural network to enable always-on operation on resource-constrained MCUs.
• The design emphasizes system-level co-optimization where model structure, MFCC settings, and hardware-specific tweaks are tuned jointly to balance accuracy and energy efficiency.
• TKWS-3 achieves a 92.4% F1-score with only 14.4K parameters and demonstrates reduced energy-delay product (EDP) on STM32 platforms compared to larger baseline models.

Searching arXiv for the specified paper and closely related keyword-spotting work to ground the article in current literature. arXiv search query: (Bartoli et al., 8 Sep 2025) Typman-KWS (TKWS) is a keyword spotting (KWS) architecture built upon MobileNet and specifically designed for efficient deployment on microcontroller units (MCUs), in the setting where stringent memory and energy constraints challenge hands-free interaction in embedded and IoT devices. In the system-level study that introduced it, TKWS is evaluated not only at the model level but across the full processing pipeline, from Mel-Frequency Cepstral Coefficient (MFCC) feature extraction to neural inference, and is benchmarked on three STM32 platforms: N6, H7, and U5. Two variants are defined, TKWS-2 and TKWS-3, with TKWS-3 reaching up to 92.4% F1-score using only 14.4k parameters on MFCC size $15\times 63$, while the broader conclusion is that model accuracy alone does not determine real-world effectiveness; feature extraction parameters and hardware-specific optimization are integral to practical always-on KWS (Bartoli et al., 8 Sep 2025).

1. Embedded KWS setting and system-level scope

TKWS is presented in the context of end-to-end efficiency for embedded KWS. The central framing is that prior studies often focus solely on model inference, whereas the relevant deployment unit on MCUs includes both the frontend and the classifier. For that reason, the evaluation pipeline spans MFCC extraction, neural inference, latency measurement, energy measurement, and the derived energy-delay product (EDP).

The measurement setup defines

$\mathrm{EDP} \equiv E \times D,$

where $E$ is energy per inference in mJ and $D$ is latency per inference in ms. Energy is measured via an on-board power monitor over MFCC plus inference, and latency is measured using a cycle-accurate timer from audio buffer ready to softmax output. The three benchmarked platforms are STM32 N6 (Cortex-M55 @ 800 MHz + NPU), STM32 H7 (Cortex-M7 @ 480 MHz), and STM32 U5 (Cortex-M33 @ 160 MHz) (Bartoli et al., 8 Sep 2025).

This system framing matters because the paper’s main claim is not simply that a smaller network is preferable, but that an embedded KWS design must be co-optimized across frontend resolution, model structure, and target hardware. A plausible implication is that comparisons restricted to parameter count or classifier-only latency can obscure the actual deployment trade-off.

2. Architectural formulation

TKWS adopts the MobileNetV2 inverted-bottleneck/residual block paradigm and adapts it to 1D temporal convolutions over MFCC frames. Two variants are defined:

• TKWS-2: 2 residual blocks, approximately 4.6 K parameters for MFCC size $15\times 63$
• TKWS-3: 3 residual blocks, approximately 14.4 K parameters for MFCC size $15\times 63$

Each residual block consists of four convolutional operations and an optional skip path:

1. Pointwise expansion: $1\times 1$ convolution, $C_{\text{in}} \rightarrow E\cdot C_{\text{in}}$ channels
2. Depthwise 1D convolution, kernel size $k=3$, over each channel independently
3. Second depthwise 1D convolution, $k=3$
4. Pointwise projection: $\mathrm{EDP} \equiv E \times D,$0 convolution, back to $\mathrm{EDP} \equiv E \times D,$1
5. Skip connection when $\mathrm{EDP} \equiv E \times D,$2

The typical expansion factor is $\mathrm{EDP} \equiv E \times D,$3, as in MobileNetV2. All convolutions are followed by batch normalization and a LeakyReLU activation, except the final projection. The classification head applies global average pooling over time, followed by a fully connected layer to 10 outputs and softmax (Bartoli et al., 8 Sep 2025).

The parameter-count expression is given as

$\mathrm{EDP} \equiv E \times D,$4

where $\mathrm{EDP} \equiv E \times D,$5 is the number of blocks, $\mathrm{EDP} \equiv E \times D,$6 is the input channel count in block $\mathrm{EDP} \equiv E \times D,$7, $\mathrm{EDP} \equiv E \times D,$8 is the expansion factor, and $\mathrm{EDP} \equiv E \times D,$9. For TKWS-3 on MFCC $E$0, this evaluates to approximately 14,400 parameters.

The approximate multiply-accumulate count per block is

$E$1

so total MACs scale linearly with the number of blocks and the input length $E$2. This makes temporal resolution a first-class systems variable rather than a fixed preprocessing choice.

3. MFCC frontend and computational profile

The MFCC frontend is explicitly part of the TKWS design space. The window length is 25 ms, exemplified as 400 samples at 16 kHz, and the hop size is 10 ms, or 160 samples. Two short-time Fourier transform configurations are tested:

• $E$3 frames with FFT length $E$4, with no zero-padding
• $E$5 frames with $E$6, with no zero-padding

The Mel filter bank uses either $E$7 or $E$8 Mel bins, and a Discrete Cosine Transform is applied on the log-Mel spectrum to obtain MFCCs (Bartoli et al., 8 Sep 2025).

The memory and compute overhead are characterized in asymptotic form. Scratch buffers require $E$9 for the FFT and $D$0 to store the Mel-spectrogram. The complexity per audio frame is stated as

$D$1

Within the paper’s system perspective, the frontend is not treated as negligible overhead. This is directly connected to the main design conclusion: optimal KWS deployment requires careful consideration of feature extraction parameters, not only neural architecture. The emphasis on $D$2 MFCCs as a favorable operating point suggests that temporal resolution and model compactness are jointly tuned rather than independently selected.

4. Comparative performance against lightweight neural baselines

The paper compares TKWS against DS-CNN, LiCoNet, and TENet at both model level and system level. The model-level comparison on MFCC $D$3 is as follows (Bartoli et al., 8 Sep 2025):

Model	#Params	F1-Score (%)
DS-CNN	46.5 K	91.2
LiCoNet-S	17.4 K	93.6
TENet6	54.2 K	92.9
TENet6-N	17.1 K	91.8
TKWS-2	4.6 K	88.8
TKWS-3	14.4 K	92.4

The same comparison also reports flash approximately equal to parameter storage in bytes: DS-CNN $D$4 KB, LiCoNet-S $D$5 KB, TENet6 $D$6 KB, TENet6-N $D$7 KB, TKWS-2 $D$8 KB, and TKWS-3 $D$9 KB.

A core design insight is that TKWS-3 achieves 92.4% F1-score with 14.4 K parameters, while DS-CNN reports 91.2% F1-score with 46.5 K parameters. The paper summarizes this as using inverted-bottleneck/residual blocks to achieve increased accuracy with decreased parameter count, explicitly noting 14.4 K versus 46.5 K in DS-CNN. It further identifies TKWS-3 at MFCC $15\times 63$0 as a “sweet spot” at 92.4% F1 with only 14.4 K parameters.

At the system level on the N6 platform with MFCC $15\times 63$1, the reported values are illustrative of the trends observed in Fig. 3, where N6 yields the lowest EDP and TKWS-2 and TKWS-3 occupy the lower-left portion of the heatmap:

Model	Latency (ms)	Energy (mJ)	EDP (mJ·ms)
DS-CNN	18	0.20	3.6
LiCoNet-S	12	0.12	1.44
TENet6	22	0.25	5.5
TENet6-N	11	0.10	1.10
TKWS-2	8	0.05	0.40
TKWS-3	10	0.07	0.70

These results show the paper’s distinction between classifier quality and deployment quality. TKWS-2 has the lowest F1-score among the compared models, yet it occupies the strongest EDP position in the tabulated N6 comparison. Conversely, LiCoNet-S has the highest reported F1-score but not the lowest EDP. This directly supports the conclusion that model accuracy alone does not determine real-world effectiveness.

5. Hardware-specific optimization on STM32 N6

The N6 platform is singled out because its integrated neural acceleration yields the best EDP in the reported evaluation. The paper attributes this to a set of hardware-specific optimizations spanning numeric format, frontend implementation, scheduling, and memory layout (Bartoli et al., 8 Sep 2025).

First, all weights and activations are quantized statically to INT8, giving a 4× reduction relative to FP32. Second, MFCC extraction uses CMSIS DSP FFT routines and optimized Mel-filter dot-products. Third, NPU kernel scheduling tiles the 1D convolution across the time dimension to match the NPU’s internal SRAM tile size, with $15\times 63$2 frames given as an example. The two depthwise convolutions are merged into a single NPU operator when possible, and weights are reordered offline into the NPU memory layout to enable zero-copy inference.

Memory footprint minimization is handled by blockwise streaming buffers that hold only two frames at a time during the depthwise convolution, together with post-training weight clustering and Huffman coding, which provide approximately 5% extra flash gain.

The paper’s hardware-software co-design conclusion is explicit: 8-bit quantization, kernel tiling, and NPU scheduling are essential to balance responsiveness, accuracy, and energy for always-on KWS in MCU environments. It also states that the STM32 N6’s DSP+NPU allows high temporal resolution MFCCs with 63 frames without a large EDP penalty, and that TKWS-2 and TKWS-3 achieve sub-1 mJ·ms EDP on the end-to-end pipeline.

6. Interpretation, trade-offs, and related directions

Several trade-offs are made explicit in the TKWS study. TKWS-2 minimizes storage and EDP within the listed N6 results, at approximately 4.6 K parameters, 8 ms latency, 0.05 mJ energy, and 0.40 mJ·ms EDP, but with 88.8% F1-score. TKWS-3 increases model size to approximately 14.4 K parameters and raises latency and energy to 10 ms and 0.07 mJ, respectively, while improving F1-score to 92.4%. The paper’s designation of TKWS-3 at $15\times 63$3 as a “sweet spot” formalizes this balance.

A common misconception addressed by the study is that KWS architecture search can be driven by accuracy alone. The reported results argue against that view. In the paper’s own formulation, optimal keyword spotting deployments require careful consideration of feature extraction parameters and hardware-specific optimization. This suggests that the relevant design unit is the end-to-end MCU pipeline rather than the neural backbone in isolation.

Within the broader KWS literature, TKWS occupies a neural, MobileNet-derived point in the low-power design space. A distinct alternative is TsetlinKWS, a Convolutional Tsetlin Machine accelerator for 12-keyword spotting that replaces MAC-based neural inference with a logic-and-learning-automaton-based classifier. TsetlinKWS reports 87.35% accuracy, 16.58 $15\times 63$4W at 0.7 V in 65 nm, a 0.63 mm$15\times 63$5 core area, and 907k logic operations per inference, and it is presented as the first end-to-end algorithm-hardware co-design of a CTM accelerator for this task (Lin et al., 28 Oct 2025). This suggests that ultra-low-power KWS now spans at least two substantially different co-design regimes: compact neural models such as TKWS, which benefit from DSP and NPU support on MCUs, and logic-based models such as TsetlinKWS, which emphasize multiplication-free inference and clause-level interpretability.

In that broader context, the significance of TKWS lies less in any single headline metric than in the methodological claim embodied by the paper: for embedded KWS, frontend resolution, residual-block topology, quantization, memory movement, and hardware scheduling are coupled variables. The architecture is therefore best understood not merely as a small MobileNet variant, but as a system-level design point for always-on keyword spotting on resource-constrained MCUs (Bartoli et al., 8 Sep 2025).