Two-Stage Flow Matching Pipeline

• Two-Stage Flow Matching Pipeline is a hybrid computational paradigm that decomposes matching problems into sequential push–relabel and cost-scaling stages.
• The first stage employs a parallel push–relabel algorithm with atomic operations on GPUs to rapidly achieve a feasible flow solution.
• The second stage refines the matching via a cost-scaling algorithm to ensure cost-optimality, making it ideal for real-time computer vision and combinatorial optimization.

A two-stage flow matching pipeline is a computational architecture and algorithmic paradigm that decomposes a flow-related graph or matching problem into two sequential, intercommunicating stages. As implemented in large-scale, parallel GPU environments, this pipeline leverages a push–relabel max-flow computation in the first stage to efficiently establish a feasible flow or matching, followed by a cost-scaling refinement stage that ensures cost-optimality for weighted matching or assignment problems. Both stages are implemented in a highly parallel, lock-free manner on devices such as Nvidia CUDA GPUs, allowing the solution of very large instances (e.g., grid or bipartite graphs) that are relevant in real-time computer vision and combinatorial optimization.

1. Parallel Push–Relabel Algorithm (Stage 1: Feasible Max-Flow Computation)

In the first stage, the pipeline applies a parallel push–relabel algorithm to solve the max-flow problem or equivalently, to compute a feasible (possibly approximate) matching or partitioning. Each node in the graph is typically mapped to a CUDA thread, allowing concurrent processing:

• Each node maintains two state variables: a height function $h(\cdot)$ and an excess function $e(\cdot)$.
• Local operations (kernel loop) for thread $x$:
  • For any outgoing residual edge $(x, y)$ where $h(x) = h(y) + 1$ and $u_f(x, y) > 0$ (residual capacity), perform a push:

  $\delta = \min\left\{ e(x), u_f(x, y) \right\}$

  $$e(x) \leftarrow e(x)-\delta,\quad e(y) \leftarrow e(y)+\delta$$

  $$u_f(x, y) \leftarrow u_f(x, y)-\delta,\quad u_f(y, x) \leftarrow u_f(y, x)+\delta$$

  Atomic operations (e.g., atomicAdd, atomicSub) are used to update shared variables across threads. - If no admissible push is possible, relabel node $x$:

  $$h(x) \leftarrow 1 + \min\{ h(y) : (x, y) \in E_f \}$$

• The CUDA kernel executes for a fixed number of CYCLE iterations per launch.
• After each kernel execution, a global relabeling occurs on the host CPU: a breadth-first search from the sink recomputes heights to improve convergence and ensure robustness against unbounded height growth, especially on difficult instances.
• Data structures (excesses, heights, capacities) reside in device global memory with local copies in shared memory for performance.
• No explicit locks are needed; correctness is ensured via atomic updates.

This parallel push–relabel approach is particularly effective for grid graphs and related computer vision problems, achieving high concurrency and memory locality.

2. Cost–Scaling Algorithm (Stage 2: Optimal Weighted Matching Refinement)

After obtaining a feasible flow, the second stage refines the solution to achieve cost-optimality for weighted matching (assignment) problems, using a parallel cost–scaling algorithm:

• Each node is assigned a thread; the node maintains a price $p(x)$ that adjusts the reduced cost of adjacent edges.
• At each iteration, the algorithm considers an adjustable parameter $\epsilon$, which is regularly decreased (e.g., $\epsilon \leftarrow \epsilon / \alpha$ for some $\alpha > 1$).
• A residual edge $(x, y)$ is admissible if its reduced cost

$c_p(x, y) = c(x, y) + p(x) - p(y)$

is less than a negative threshold (e.g., $-\frac{1}{2}\epsilon$).

• For admissible edges, push operations (unit capacities) update excesses and residual capacities atomically.
• If no admissible push exists, relabel (update price) of node $x$:

$$p(x) \leftarrow -\min_{(x, z) \in E_f}(c(x, z) - p(z) + \epsilon)$$

• As in the first stage, atomic operations avoid locks, and the kernel executes for fixed iteration windows with host-side synchronization as required.

The $\epsilon$-optimality condition is maintained throughout:

$c_p(x, y) \geq -\epsilon,~\forall~(x, y)\in E_f$

Cost scaling iteratively tightens this condition, producing an optimal assignment (matching) when $\epsilon < 1/n$.

The following table summarizes the core data structures and atomic operations:

Variable	Purpose	Atomic Update Needed
$e(x)$	Node excess	Yes
$h(x)$	Node height	Yes
$u_f(x, y)$	Edge residual capacity	Yes
$p(x)$	Node price	Yes

3. Interfacing the Two Stages

The explicit coupling of stages enables an effective pipeline:

1. Stage 1 (Push–relabel): Solves for a feasible (approximate) matching with high concurrency.
2. Stage 2 (Cost–scaling): Refines the feasible solution from Stage 1 into a minimum-cost (assignment) solution by iteratively adjusting prices and saturating cost-effective edges.

The same CUDA kernels, with slight modifications (notably to update price and cost structures), can be reused across both stages. Host-device data transfer is minimized by organizing all state arrays in contiguous memory and performing bulk synchronization at kernel restarts.

Hybrid CPU–GPU control is critical for large graphs and ensures resilience against GPU time-out and numeric instability.

4. Numerical Stability, Synchronization, and Scalability Challenges

Key parallelization and scaling challenges include:

• Synchronization: Massive concurrency is achieved via atomic operations; careful design is required to avoid deadlocks and ensure correct updates even when many threads target the same node or edge.
• Host synchronization: The termination of CUDA kernels after a fixed CYCLE ensures host intervention for expensive global computations (e.g., global relabeling or global price updates).
• Memory management: Arrays for heights, excesses, prices, and capacities are stored in device memory, with critical data staged into fast shared memory per block for performance.
• Load balancing: For graphs with irregular degree distributions, thread divergence and unbalanced load may affect throughput.

Resource constraints (e.g., available device memory for problem sizes up to ~10⁵–10⁶ nodes) and device/host transfer requirements are primary bottlenecks.

5. Mathematical and Implementation Formulations

The principal update formulas, as used in CUDA kernels, are:

Push operation:

$$\delta = \min\{ e(x), u_f(x, y) \} \ e(x) \leftarrow e(x)-\delta, \quad e(y) \leftarrow e(y)+\delta \ u_f(x, y) \leftarrow u_f(x, y)-\delta, \quad u_f(y, x) \leftarrow u_f(y, x)+\delta$$

Reduced cost for cost-scaling:

$c_p(x, y) = c(x, y) + p(x) - p(y)$

Price update:

$$p(x) \leftarrow -\min_{(x, z)\in E_f} \{ c(x, z) - p(z) + \epsilon \}$$

These operations are embedded within GPU kernels, each thread operating on a node and accessing appropriate edges using global or shared arrays.

6. Application Scenarios and Practical Considerations

This two-stage flow matching pipeline is well-suited for large-scale real-time applications, including:

• Image segmentation and energy minimization in computer vision, where rapid graph cuts and min-cost matchings are required.
• Large graph assignment problems in transport, vision, or logistical planning, benefiting from massive parallel hardware.
• Any setting where initial rapid feasibility is followed by high-precision cost optimization.

The combined pipeline supports thousands of concurrent threads, allowing large volumes of data to be processed efficiently, with optimized memory layout, robust host-device synchronization, and avoidance of thread contention via lock-free atomic designs.

Potential limitations include:

• The need to balance kernel cycle length (CYCLE parameter) with host-side global relabeling frequency for convergence and robustness.
• Synchronization points introducing possible bottlenecks if load balancing is poor or if host-device transfers are excessive.

7. Summary

The two-stage flow matching pipeline integrates a hybrid parallel push–relabel method for initial feasible matching with a cost-scaling assignment refinement, both realized in a massively parallel, lock-free CUDA implementation. With atomic updates, careful memory architecture, and hybrid host-device control, the pipeline achieves both performance and scalability, enabling efficient solution of grid-based and bipartite matching problems at unprecedented scales. This architectural separation facilitates robust, high-throughput solutions for max-flow and assignment problems critical in computer vision and combinatorial optimization domains (Łupińska, 2011).