TopoSizing: Topology-Aware Sizing Optimization

• TopoSizing is a topology-aware design methodology that establishes qualitative structural representations to guide subsequent geometric sizing and simplification.
• It employs intermediate models such as persistence pairs and bipartite circuit graphs to reduce design complexity while ensuring manufacturability and structural fidelity.
• The approach combines advanced controls—including topology-first smoothing, error-bounded compression, and LLM-guided parameter tuning—to achieve significant efficiency gains in design optimization.

TopoSizing denotes a topology-aware approach to reduction, control, and parameter assignment in which qualitative or structural organization is established before, or jointly with, geometric sizing, feature retention, or search-space restriction. In current arXiv literature, the name appears explicitly in an LLM-aided framework for analog and mixed-signal circuit sizing from raw netlists (Wei et al., 17 Sep 2025), and closely related papers use the term as a broader perspective for topology-first smoothing, additive-manufacturing-aware topology optimization, post-optimization structural editing, topology-preserving compression, topology-first space planning, and topology-informed prototype selection (Rosen et al., 2019). The common theme is that the quantity being “sized” is not treated as an unstructured numerical variable alone: salient extrema, module-stage hierarchy, nozzle width, contour-tree arcs, layout adjacencies, or structural characteristics are first made explicit, and downstream sizing or simplification is then constrained by that structure.

1. Meanings and research scope

Across the cited literature, TopoSizing is not a single algorithm but a family resemblance among topology-first workflows. In the narrowest sense, it is the title of “TopoSizing: An LLM-aided Framework of Topology-based Understanding and Sizing for AMS Circuits” (Wei et al., 17 Sep 2025). In a broader sense, several papers explicitly motivate their methods as relevant to a “TopoSizing” perspective: TopoLines treats smoothing level as the “percent of local extrema removed,” so simplification is specified in terms of a topological feature budget rather than kernel width or spectral cutoff (Rosen et al., 2019); the LSAM paper develops a nozzle-size-aware topology sizing strategy in which minimum member size, maximum member size, and minimum cavity size are tied to the deposition nozzle (Fernández et al., 2021); and space-planning work separates “topological solutions” from later geometric instantiation, making topology an equivalence class over realizable layouts (Medjdoub et al., 2013).

Domain	TopoSizing role	Representative paper
AMS circuits	Topology-based understanding and sizing from raw netlists	(Wei et al., 17 Sep 2025)
Line-chart smoothing	Simplification by persistence-pair budget	(Rosen et al., 2019)
Large-scale additive manufacturing	Nozzle-size-aware topology sizing	(Fernández et al., 2021)
Post-optimization editing	Characteristic-guided topology control	(Chen et al., 27 Mar 2026)
Scientific compression	Topology-preserving error-bounded compression	(Yan et al., 2023)
Space planning	Topology-first then geometry/sizing	(Medjdoub et al., 2013)

A recurrent distinction in this literature is between topology-aware control and purely geometric or purely numerical reduction. TopoLines does not optimize smoothness in the same sense as Gaussian filtering or Douglas–Peucker; rather, persistence determines which extrema survive and isotonic regression reconstructs the least-squares-consistent shape (Rosen et al., 2019). The LSAM methods do not merely impose a minimum feature size; they also impose a maximum member size so that members are compatible with a discrete number of deposited beads (Fernández et al., 2021). TopoSZ does not rely on a single pointwise error budget; it derives local admissible intervals from contour-tree-induced segmentation and then constrains quantization by those intervals (Yan et al., 2023).

2. Topology-first representations

A central TopoSizing pattern is the construction of an intermediate structural representation that is richer than a raw geometry yet coarser than a fully dimensioned realization. In ARCHiPLAN, a “topological solution” is defined as a space-layout CSP in which the $n.(n-1)/2$ non-overlapping variables and adjacency variables are instantiated and which remains geometrically consistent, meaning that at least one geometrical solution exists (Medjdoub et al., 2013). The result is an equivalence class of geometrical solutions that share the same relative orientation conditions among spaces. This explicitly separates qualitative arrangement from exact dimensional assignment.

In TopoLines, the intermediate representation is the persistence pairing of extrema in a 1D function $f:\mathcal{K}\rightarrow\mathbb{R}$. The method computes a lower-star filtration of a 1D simplicial complex, builds a merge tree, and outputs persistence pairs

$C=\{[b_0,d_0), [b_1,d_1), \ldots, [b_m,d_m)\},$

with persistence

$p_i = |f(d_i)-f(b_i)|.$

This representation ranks minima/maxima by salience and enables simplification by removing low-persistence pairs via a threshold $t$ or a fraction $q$ of least persistent pairs (Rosen et al., 2019). The retained extrema and boundary points then act as hard structural anchors.

In TopoSZ, the corresponding representation is the contour tree of a scalar field and its contour-tree-induced segmentation. For a contour-tree edge $e$ with endpoints $a,b$ and $f(a)>f(b)$, regular points in $\phi^{-1}(e)$ are assigned topology-derived admissible intervals

$f:\mathcal{K}\rightarrow\mathbb{R}$0

while critical points are frozen with $f:\mathcal{K}\rightarrow\mathbb{R}$1 (Yan et al., 2023). This converts global topological relations into pointwise local constraints used during compression.

The AMS-circuit framework named TopoSizing constructs a hierarchical circuit abstraction rather than a geometric complex. A raw netlist is transformed into a bipartite graph

$f:\mathcal{K}\rightarrow\mathbb{R}$2

with labeled edges indicating terminal roles, then recurring analog modules are detected by subgraph isomorphism and collapsed into supernodes, and a current-conduction graph is used to partition the design into stages (Wei et al., 17 Sep 2025). This produces the device-level, module-level, and stage-level hierarchy on which LLM reasoning is performed.

3. Sizing and control mechanisms

Once topology has been extracted, TopoSizing methods differ mainly in how they convert structural information into explicit control variables. In the LSAM work, the base formulation is density-based SIMP with the robust three-field formulation of eroded, intermediate, and dilated realizations. The density filter is

$f:\mathcal{K}\rightarrow\mathbb{R}$3

with

$f:\mathcal{K}\rightarrow\mathbb{R}$4

followed by the smoothed Heaviside projection

$f:\mathcal{K}\rightarrow\mathbb{R}$5

Maximum member-size control is then imposed through the local void-fraction restriction

$f:\mathcal{K}\rightarrow\mathbb{R}$6

aggregated globally by a $f:\mathcal{K}\rightarrow\mathbb{R}$7-mean (Fernández et al., 2021). Method 1, the nozzle size constraint, sets minimum and maximum member size to approximately the nozzle-scaled target, while Method 2, skeleton-based deposition paths, constrains the intermediate field and then thickens it to a printable AM field.

TopoCtrl uses a different control mechanism: the topology has already been optimized, and the task is post-optimization editing toward target structural characteristics. A pre-trained latent diffusion model encodes a topology $f:\mathcal{K}\rightarrow\mathbb{R}$8 to $f:\mathcal{K}\rightarrow\mathbb{R}$9, partial noising produces

$C=\{[b_0,d_0), [b_1,d_1), \ldots, [b_m,d_m)\},$0

and regression-guided denoising minimizes the mismatch between a latent regressor prediction and a desired characteristic target via

$C=\{[b_0,d_0), [b_1,d_1), \ldots, [b_m,d_m)\},$1

The controlled characteristics are the number of joints, the maximum number of members connected to a joint, the characteristic member length, and thickness, all measured by a medial-axis-based post-processing pipeline (Chen et al., 27 Mar 2026). This suggests a TopoSizing regime in which sizing targets are evaluator-defined structural statistics rather than native design variables.

TopoLines uses topological persistence itself as the sizing knob. The simplification stage removes

$C=\{[b_0,d_0), [b_1,d_1), \ldots, [b_m,d_m)\},$2

or

$C=\{[b_0,d_0), [b_1,d_1), \ldots, [b_m,d_m)\},$3

after which isotonic regression reconstructs the least-squares-consistent monotone segments between retained extrema (Rosen et al., 2019). TopoSZ uses the pair $C=\{[b_0,d_0), [b_1,d_1), \ldots, [b_m,d_m)\},$4 as dual control parameters: $C=\{[b_0,d_0), [b_1,d_1), \ldots, [b_m,d_m)\},$5 is a global pointwise error bound, while $C=\{[b_0,d_0), [b_1,d_1), \ldots, [b_m,d_m)\},$6 is the persistence threshold determining which topological features of the simplified field must be preserved (Yan et al., 2023).

A related but distinct sizing mechanism appears in TopoNAS, where the object being reduced is the search graph itself. Partial Module Sharing and Floating Module Sharing simplify repeated subgraphs on searchable edges, after which the remaining kernels can be reparameterized; kernel normalization

$C=\{[b_0,d_0), [b_1,d_1), \ldots, [b_m,d_m)\},$7

is used to reduce the bilinear coupling between architecture parameters and kernels (Zhao et al., 2024). This suggests a TopoSizing interpretation in which search-space size is reduced by graph simplification before or during optimization.

4. The AMS-circuit framework named TopoSizing

The paper that explicitly bears the name TopoSizing addresses analog and mixed-signal device sizing under expensive simulation and topology-dependent design spaces. Its input is a raw netlist; its output is a feasible or optimized set of design parameters for circuits such as a two-stage OTA, a folded-cascode OTA, a StrongArm latch comparator, and an LDO (Wei et al., 17 Sep 2025).

The framework begins with topology extraction. The netlist is converted into a labeled bipartite circuit graph whose device nodes include NMOS, PMOS, $C=\{[b_0,d_0), [b_1,d_1), \ldots, [b_m,d_m)\},$8, $C=\{[b_0,d_0), [b_1,d_1), \ldots, [b_m,d_m)\},$9, $p_i = |f(d_i)-f(b_i)|.$0, and $p_i = |f(d_i)-f(b_i)|.$1, and whose net nodes include net, GND, and VDD. Known analog building blocks such as differential pairs, current mirrors, cascode stages, cascode current mirrors, class-AB stages, and diode-connected MOS devices are detected by subgraph isomorphism and replaced by supernodes. A current-conduction graph is then formed by removing non-current-carrying edges, and VDD-to-GND conduction paths are merged into stage groupings through the equivalence relation

$p_i = |f(d_i)-f(b_i)|.$2

yielding a stage graph over $p_i = |f(d_i)-f(b_i)|.$3 (Wei et al., 17 Sep 2025).

LLM agents then operate on this structured hierarchy in an iterative hypothesis–verification–refinement loop with built-in consistency checks. The explicit purpose is to infer device roles, module functions, stage functions, connectivity consistency, and symmetry-aware parameter-tying opportunities. The optimization stage uses TuRBO as the BO backbone. For feasibility, the paper defines

$p_i = |f(d_i)-f(b_i)|.$4

so a feasible design satisfies $p_i = |f(d_i)-f(b_i)|.$5. For constrained single-objective optimization, positive target reward is granted only after all non-target specifications are satisfied (Wei et al., 17 Sep 2025).

The paper injects topology understanding into BO in two places. First, it performs conservative initial-space pruning and LLM-guided initial sampling; one example given is the heuristic $p_i = |f(d_i)-f(b_i)|.$6 for a differential pair. Second, it performs stagnation-triggered trust-region updates inside TuRBO. If the best observed performance does not improve for $p_i = |f(d_i)-f(b_i)|.$7 consecutive iterations, the LLM analyzes optimization history and topology annotations and proposes a new trust-region center $p_i = |f(d_i)-f(b_i)|.$8 and radius $p_i = |f(d_i)-f(b_i)|.$9 (Wei et al., 17 Sep 2025).

Empirically, the framework reports 100% correctness in circuit understanding and 100% correctness in parameter assignment across the four benchmark circuits. Relative to conventional baselines, the reported sample-count improvement ranges from 1.4× to 4.8×, runtime speedup from 1.2× to 3.5×, and relative to prior LLM-aided baselines the framework uses roughly 2–4× fewer LLM calls (Wei et al., 17 Sep 2025). The paper’s own interpretation is that these optimization gains depend directly on the quality of topology understanding.

5. Representative extensions and infrastructural relations

Several papers extend the TopoSizing idea beyond direct sizing of design parameters. In 3D Raman-emitter design, topology optimization is organized around distributed emitters, random molecular orientations, and manufacturable minimum-lengthscale geometries. The design variable is a density field $t$0, which is filtered, projected by subpixel-smoothed projection, and mapped to permittivity, while minimum linewidth constraints of $t$1 are imposed on both solid and void phases (Hammond et al., 30 Jan 2026). The objective is the spatially averaged Raman signal in the trace form

$t$2

The paper’s main TopoSizing lesson is that lengthscale control is both a fabrication constraint and a mathematical regularizer, because otherwise the $t$3-type SERS objective can drive the design toward singular tips (Hammond et al., 30 Jan 2026).

In prototype selection, TPS uses persistent homology of a sliced bifiltration to select representative training instances. For each target class, a neighbor filtration captures inter-class topology, a radius filtration captures intra-class topology, and the prototype set is the vertex set of the chosen subcomplex. The lifetime criterion

$t$4

is used together with a quantile selection in the neighbor stage and a mean-lifetime selection in the radius stage (Eckert et al., 6 Nov 2025). This is not model sizing, but it is a topology-informed form of dataset sizing.

One infrastructural relation is especially important for optimization-centric uses of TopoSizing. “Topological Optimization of the Evaluation of Finite Element Matrices” is explicitly not a topology optimization or sizing optimization paper in the design sense; it is a graph-theoretic method for reducing arithmetic in finite element local tensor evaluation (Kirby et al., 2012). The central representation is

$t$5

and complexity-reducing relations between reference-tensor slices are optimized through a minimum spanning tree. The paper is therefore peripheral to TopoSizing in the design sense, but potentially important as an acceleration mechanism for repeated FE assembly inside iterative topology/sizing loops (Kirby et al., 2012).

A similar distinction applies to TopoSZ and TopoNAS. TopoSZ is not sizing optimization; it is topology-preserving error-bounded compression with strict pointwise error control and contour-tree-derived admissible value intervals (Yan et al., 2023). TopoNAS is not topology design; it is search-efficiency improvement by simplifying the topology of searchable paths in one-shot NAS (Zhao et al., 2024). Both nevertheless fit a broader TopoSizing interpretation in which topological structure defines how much information or computation is retained.

6. Limitations, misconceptions, and open directions

A recurrent misconception is that “topological” always means topology optimization of a structure. One paper states explicitly that “Topological Optimization of the Evaluation of Finite Element Matrices” is about graph topology and arithmetic reuse, not topology or size optimization of material distributions (Kirby et al., 2012). Another misconception is that topological salience is automatically equivalent to semantic importance. TopoLines reports strong results on retrieve-value tasks and on find-extrema tasks for astronomy and climate data, but “mostly unremarkable” performance on EEG and stock data, with the stated explanation that those signals contain high-frequency noise producing many extrema that persistence still tries to preserve (Rosen et al., 2019).

Most TopoSizing-style methods also rely on thresholds or proxies that define which structure matters. TopoSZ preserves the topology of the $t$6-simplified field, not all topology exactly, and iteratively refines local bounds until false positives, false negatives, and false types disappear in the simplified contour tree (Yan et al., 2023). TPS is metric dependent, hyperparameter sensitive, and uses a heuristic ExtractVertices stage to recover retained samples from persistence features (Eckert et al., 6 Nov 2025). TopoCtrl provides approximate characteristic control rather than hard guarantees; its edited structures remain coherent under the OAT prior, but the paper explicitly states that it is not a new physics-constrained re-optimization and reports best-of-64 failure rates from 4.67% to 16.00% depending on the task (Chen et al., 27 Mar 2026).

Manufacturability-aware TopoSizing is also incomplete in several domains. In the LSAM paper, neither method solves full path planning; both still show small unfilled regions at intersections, local maximum-size violations can persist because the global restriction is a smooth $t$7-mean aggregation, and Method 2 cannot guarantee minimum cavity size in the final AM field because the printable structure is obtained by dilation (Fernández et al., 2021). In the Raman-emitter work, the superiority of metallic designs over dielectrics is framed as a practical conclusion for $t$8, not as a universal statement; the paper explicitly notes that very-high-$t$9 dielectric regimes may require larger cells, better initialization, and may be much more fabrication sensitive (Hammond et al., 30 Jan 2026).

The open directions identified across the literature are correspondingly diverse. The AMS-circuit TopoSizing framework would benefit from broader topology coverage and further formalization of LLM consistency checks (Wei et al., 17 Sep 2025). The LSAM work suggests future combinations with overhang constraints, post-machining constraints, and uncertainty modeling on bead width (Fernández et al., 2021). TopoCtrl proposes extending characteristic control to additional measures such as number of holes and minimum angles between members, and moving to 3D once a 3D topology foundation model becomes available (Chen et al., 27 Mar 2026). TopoSZ suggests extending topology-preserving compression beyond contour trees toward descriptors such as Morse-Smale complexes (Yan et al., 2023). Taken together, these directions suggest that TopoSizing is evolving less as a fixed method than as a general research program: topology is first made explicit, then sizing, simplification, or optimization is performed under that topological model.