Timed FSMs with Output Delays

• Timed FSMs with output delays are automata models where transitions are decoupled from the immediate emission of outputs, using buffering or timed dispatch to handle delays.
• They are formalized through frameworks like ADBs and dense-time TFSMs, which employ discrete and continuous time domains to capture delay semantics and enable finite abstractions.
• These models exhibit enhanced expressiveness, allowing non-regular untimed behaviors, and require specialized methodologies for deriving synchronizing and homing sequences in verification.

Searching arXiv for recent and foundational work on timed FSMs with output delays. arXiv search query: "timed finite state machines with output delays automata with delay blocks timed automata polynomial delay" Timed finite-state machines with output delays are automata-theoretic models in which the transition that is triggered by an input and the output that becomes observable need not occur at the same time. In the literature, this phenomenon is formalized in several ways: as discrete-time buffering of transition outputs in Automata with Delay Blocks (ADBs), as dense-time deterministic Timed FSMs (TFSMs) whose transitions carry both timed guards and positive integer output delays, as single-clock timed machines with guards and timeouts that admit finite untimed abstractions, and as runtime-verification models that account for unknown communication latency between a system and its monitor. Taken together, these frameworks show that delayed emission substantially changes expressiveness, closure properties, decision problems, and state-identification procedures (Chatterjee et al., 2012, Vinarskii et al., 19 Jul 2025, Bresolin et al., 2021, Fränzle et al., 2024, Bura et al., 2017).

1. Model families

A concise way to organize the area is to distinguish the time domain, the source of delay, and whether the model is generative or transductive.

Model	Time domain	Delay mechanism
ADB	discrete time	transition label $(\sigma,\block{t})$, plus $\tick$ transitions
TFSM with timed guards and timeouts	dense time	timed guards and timeout function, no explicit output delay
TFSM with output delays	dense time	transition $s\xrightarrow{i,g/o,d}s'$ produces $o$ at time $t+d$
delayed-output PTA/TBA monitoring	dense time	unknown latency $\delta\in[l,u]$ and jitter $\epsilon$ in observation

In ADBs, an automaton is a 6-tuple

$\A=(L,\Sigma,\tick,D,\delta,l_s,L_f),$

where $D=\{\block{0},\block{1},\dots,\block{M}\}$ is a finite set of delay blocks, $\tick\notin\Sigma$ advances global discrete time by one unit, and an output-delay transition $\tick$0 means that $\tick$1 is buffered and emitted exactly $\tick$2 time units later. In dense-time TFSMs with output delays, the machine is

$\tick$3

where timed guards $\tick$4 constrain elapsed time between consecutive inputs and each transition $\tick$5 associates an output symbol $\tick$6 with a positive integer delay $\tick$7. In the neighboring single-clock TFSM model with timed guards and timeouts, transitions are immediate but states carry a timeout function $\tick$8, which induces spontaneous clock-resetting transitions when a timeout bound is reached. For runtime verification under delayed observation, the delay is not attached to the system transition itself; instead, the monitor introduces auxiliary clocks $\tick$9 and $s\xrightarrow{i,g/o,d}s'$0, with unknown latency represented by $s\xrightarrow{i,g/o,d}s'$1 and refined by per-event jitter constraints (Chatterjee et al., 2012, Vinarskii et al., 19 Jul 2025, Bresolin et al., 2021, Fränzle et al., 2024).

2. Discrete-time delayed emission

The ADB model gives the cleanest formal account of delayed output in a finite-state setting. A generating run is a finite sequence

$s\xrightarrow{i,g/o,d}s'$2

with $s\xrightarrow{i,g/o,d}s'$3, $s\xrightarrow{i,g/o,d}s'$4, and each label $s\xrightarrow{i,g/o,d}s'$5 drawn from $s\xrightarrow{i,g/o,d}s'$6. Time starts at $s\xrightarrow{i,g/o,d}s'$7 and increases only when a $s\xrightarrow{i,g/o,d}s'$8 transition occurs, except that one final virtual tick flushes buffered outputs at the end of an accepting run. If $s\xrightarrow{i,g/o,d}s'$9 is taken when current time is $o$0, the machine enqueues $o$1. All events stamped with the same time are emitted simultaneously, preserving generation order. The timed word is obtained by stably sorting all generated events by timestamp; the untimed language is the projection $o$2 onto $o$3 (Chatterjee et al., 2012).

This buffering semantics is already sufficient to produce non-regular and even non-context-free untimed behavior. The standard example is an ADB over $o$4 with one control location and self-loops labeled $o$5, $o$6, and $o$7. A run generating the regular pattern $o$8 produces all $o$9's at time $t+d$0, all $t+d$1's at time $t+d$2, and all $t+d$3's at time $t+d$4, so

$t+d$5

The significance of the example is methodological as well as language-theoretic: it shows that delaying outputs can increase expressive power without adding a stack, counters, or general-purpose memory (Chatterjee et al., 2012).

A common misconception is that delayed-output automata merely re-encode ordinary timed words. The ADB example shows otherwise. The run itself can remain structurally regular, while the buffered emission discipline induces a non-regular untimed projection. The source of additional expressiveness is therefore the reordering and deferred release of outputs, not state-space growth in the control graph.

3. Dense-time transduction and finite abstractions

In dense-time TFSMs with output delays, a timed input is a sequence

$t+d$6

The sequence is enabled at an initial state $t+d$7 if there is a run

$t+d$8

where each step uses a transition $t+d$9, the inter-arrival difference $\delta\in[l,u]$0 satisfies $\delta\in[l,u]$1, and the output $\delta\in[l,u]$2 is produced at time $\delta\in[l,u]$3, with $\delta\in[l,u]$4. Intermediate inputs may overlap in time with pending outputs; the observed response is therefore obtained by reordering the pairs $\delta\in[l,u]$5 into non-decreasing order by $\delta\in[l,u]$6. Determinism is defined by disjointness of guards for a fixed state and input, and Proposition 2.1 states that if $\delta\in[l,u]$7, then $\delta\in[l,u]$8 is always a single state (Vinarskii et al., 19 Jul 2025).

A major technical theme is the reduction of timed behavior to finite untimed structure. For deterministic single-clock TFSMs with timed guards and timeouts, one defines a time-abstract untimed FSM

$\delta\in[l,u]$9

where $\epsilon$0 partitions the nonnegative reals into point intervals $\epsilon$1, open unit intervals $\epsilon$2, and $\epsilon$3. The natural relation

$\epsilon$4

is a $\epsilon$5-bisimulation, implying

$\epsilon$6

for every timed input $\epsilon$7. As a consequence, two such TFSMs are equivalent if and only if their untimed abstractions are equivalent as ordinary FSMs, and their intersection can be built by untiming, intersecting, and refining back to a TFSM (Bresolin et al., 2021).

For TFSMs with output delays, the corresponding abstraction is input-guard sensitive. The construction $\epsilon$8 uses untimed inputs of the form $\epsilon$9 drawn from a refined partition of all guards for $\A=(L,\Sigma,\tick,D,\delta,l_s,L_f),$0, and outputs of the form $\A=(L,\Sigma,\tick,D,\delta,l_s,L_f),$1. Lemma 4.1 states that $\A=(L,\Sigma,\tick,D,\delta,l_s,L_f),$2 is deterministic, complete, polynomial in $\A=(L,\Sigma,\tick,D,\delta,l_s,L_f),$3, and preserves domains and next-state behavior: $\A=(L,\Sigma,\tick,D,\delta,l_s,L_f),$4 This finite abstraction underlies polynomial-time decision procedures for synchronizing and homing in important subclasses (Vinarskii et al., 19 Jul 2025).

4. Expressiveness, closure, and decidability

For ADBs, the expressiveness picture is sharp. Every regular language $\A=(L,\Sigma,\tick,D,\delta,l_s,L_f),$5 can be realized as $\A=(L,\Sigma,\tick,D,\delta,l_s,L_f),$6 by replacing each NFA transition $\A=(L,\Sigma,\tick,D,\delta,l_s,L_f),$7 with $\A=(L,\Sigma,\tick,D,\delta,l_s,L_f),$8. At the same time, the untimed ADB languages strictly contain the regular languages and are incomparable with the context-free languages: $\A=(L,\Sigma,\tick,D,\delta,l_s,L_f),$9 is generated by an ADB, but a deterministic visibly-pushdown language such as balanced parentheses is not of the form $D=\{\block{0},\block{1},\dots,\block{M}\}$0 for any ADB. Thus delayed output does not simply recover context-freeness; it yields a distinct intermediate family (Chatterjee et al., 2012).

The closure theory is similarly asymmetric. Untimed ADB languages are closed under union, concatenation, Kleene star, and intersection with regular languages, and the corresponding constructions are polynomial time if the maximum delay is viewed as constant. They are not closed under intersection with other ADB languages and not closed under complementation. Decision-theoretically, emptiness of $D=\{\block{0},\block{1},\dots,\block{M}\}$1 can be decided in time $D=\{\block{0},\block{1},\dots,\block{M}\}$2 by reachability in the control graph, and membership of a given timed word can be decided in time

$D=\{\block{0},\block{1},\dots,\block{M}\}$3

for an ADB with $D=\{\block{0},\block{1},\dots,\block{M}\}$4 states, $D=\{\block{0},\block{1},\dots,\block{M}\}$5 transitions, maximum delay $D=\{\block{0},\block{1},\dots,\block{M}\}$6, and a timed word whose largest timestamp is $D=\{\block{0},\block{1},\dots,\block{M}\}$7. By contrast, universality of $D=\{\block{0},\block{1},\dots,\block{M}\}$8 is undecidable, while containment of an ADB language in a regular language is PSPACE-complete when $D=\{\block{0},\block{1},\dots,\block{M}\}$9 is fixed (Chatterjee et al., 2012).

A broader continuous-time line of work introduces Timed Automata with Polynomial Delay and characterizes their expressiveness relative to previous models of Timed, Probabilistic and Stochastic Timed Automata. The abstract formulation indicates a move from fixed or bounded-delay mechanisms to transition delays determined by polynomial structure, although the high-level published statement is limited to the introduction of the model and the expressiveness comparison (Bura et al., 2017).

5. Homing and synchronizing sequences

State identification in TFSMs with output delays requires adapting classical FSM notions to delayed, time-stamped responses. A timed input sequence $\tick\notin\Sigma$0 merges two states $\tick\notin\Sigma$1 if it is enabled at both and

$\tick\notin\Sigma$2

It is synchronizing if there exists $\tick\notin\Sigma$3 such that

$\tick\notin\Sigma$4

for every state $\tick\notin\Sigma$5. It is homing if equality of timed-output responses forces merging: $\tick\notin\Sigma$6 As in untimed machines, every synchronizing sequence is a homing sequence, but not conversely (Vinarskii et al., 19 Jul 2025).

The delayed-output setting changes several classical intuitions. Merging sequences remain merging under any prolongation, and synchronizing sequences are stable under prolongation. Homing sequences, however, need not be stable under right- or left-prolongation. The paper identifies the precise obstruction: failure occurs when two input timestamps differ by an integer. If one restricts attention to non-integer timed sequences, meaning $\tick\notin\Sigma$7 for all $\tick\notin\Sigma$8, then homing becomes stable under prolongation again. This is a substantial departure from the untimed theory and one of the clearest examples of how delayed output timestamps alter the combinatorics of testing and diagnosis (Vinarskii et al., 19 Jul 2025).

Two derivation methods are emphasized. The truncated successor-tree method applies to deterministic weakly-complete TFSMs with integer guards. It explores canonical timed inputs $\tick\notin\Sigma$9, where $\tick$00 ranges over the union of all guards for $\tick$01 and $\tick$02 is fixed non-integer. The tree depth is at most $\tick$03, terminal singleton partitions witness homing, and repeated partitions witness failure along a branch. The FSM-abstraction method applies to TFSMs with left-closed right-open guards $\tick$04, builds $\tick$05 in time $\tick$06, and then invokes standard polynomial-time FSM procedures. The resulting complexity landscape is mixed: existence of HSs and SSs in the left-closed right-open class is in $\tick$07; any shortest HS has length $\tick$08, any shortest SS has length $\tick$09; derivation of a shortest HS or SS is NP-hard; and for partial point-interval TFSMs with polynomially bounded delays, checking HS existence is PSPACE-complete. For general TFSMs with arbitrary guards, decidability and complexity of HS existence remain open (Vinarskii et al., 19 Jul 2025).

6. Runtime verification and broader delay formalisms

An important adjacent problem is delayed observation rather than delayed generation. In online monitoring of real-time systems, the monitor often cannot assign exact timestamps to observed actions because the communication path introduces substantial and fluctuating parametric delays. The delayed-output PTA/TBA approach models this by adding two monitor clocks, $\tick$10 and $\tick$11, so that the unknown constant latency is represented by

$\tick$12

and per-event jitter is bounded by $\tick$13. Zone semantics are maintained in a DBM over the original system clocks plus these auxiliary clocks. When the monitor observes an event at time $\tick$14, it refines the symbolic state using

$\tick$15

The algorithm is purely zone-based and does not recur to costly verification procedures for parametric timed automata (Fränzle et al., 2024).

The verification result is exact: the zone monitor returns $\tick$16 iff every system extension consistent with the delay bounds satisfies the property automaton, returns $\tick$17 iff every such extension violates it, and otherwise returns an inconclusive verdict. Termination follows from the standard DBM-extrapolation argument, since only finitely many distinct zones can appear. The implementation was built in C++ on top of UPPAAL’s DBM library and evaluated on six response-time properties of an industrial gear-controller model with up to $\tick$18 observations. Under delay $\tick$19 and jitter $\tick$20, the maximal per-event reaction time remained below $\tick$21 ms, while the number of symbolic states grew from $\tick$22 at $\tick$23 observations to $\tick$24 at $\tick$25; in the delay-free case, the zone-set size remained constant at $\tick$26 (Fränzle et al., 2024).

This line of work clarifies a distinction that is sometimes blurred. In TFSMs and ADBs, the delay belongs to the modeled machine: a transition occurs now, but its output is scheduled for later. In runtime verification under parametric communication delays, the system may emit immediately, yet the monitor receives the event later. The mathematical techniques overlap—timed words, symbolic zones, abstractions—but the semantic location of the delay is different. A plausible implication is that future unifications of these approaches will need to separate at least three timing layers: state evolution, output scheduling, and observation latency.

Open directions stated in the literature include extending ADB-style ideas to continuous time or real-valued delays, studying probabilistic delays and costs, handling arbitrary real guards beyond integer endpoints, dealing with unobservable output timestamps, and homing to a timed configuration consisting of state plus pending jobs rather than to a single state (Chatterjee et al., 2012, Vinarskii et al., 19 Jul 2025).