Temporal Logic Task Specifications

• Temporal logic task specifications are formal frameworks that define system behaviors over time using temporal operators and state predicates.
• They integrate discrete planning via SAT/SMT encodings with continuous motion planning using LP synthesis, ensuring efficient trajectory generation.
• This approach offers soundness and completeness guarantees, making it well-suited for safety-critical and autonomous system applications.

Temporal logic task specifications provide a rigorous framework for describing, analyzing, and synthesizing behaviors of dynamical systems—especially in safety-critical or autonomous domains. These specifications articulate complex task requirements as formulas over state predicates using temporal operators, enabling formal reasoning about sequencing, constraints, and correctness of high-level tasks. Modern approaches integrate temporal logic into controller and trajectory synthesis, leveraging discrete planning (via SAT/SMT or automata) alongside continuous motion planning (via LP, MILP, or sampling), with proven guarantees on soundness, completeness, and scalability for both convex and non-convex task classes (Silva et al., 2020).

1. Formal Syntax and Semantics of Temporal Logic Task Specifications

Temporal logic task specifications delimit allowable system trajectories by encoding constraints as temporal formulas over state predicates. In "Automatic Trajectory Synthesis for Real-Time Temporal Logic" (Silva et al., 2020), the logic employed is Real-Time Temporal Logic (RTL), an expressive fragment characterized by:

• Atomic predicates: Linear-affine constraints $\pi : h^\top x + a > 0$, where $x \in \mathbb{R}^n$ is the system state.
• State-formula syntax:
  • $$\psi ::= \pi \mid \lnot \pi \mid \psi_1 \land \psi_2 \mid \psi_1 \lor \psi_2$$
• Path-formula syntax:
  • $$\varphi ::= \psi \mid \lnot \psi \mid \varphi_1 \land \varphi_2 \mid \varphi_1 \lor \varphi_2 \mid \varphi_1 U \varphi_2 \mid \varphi_1 R \varphi_2$$
• Temporal operators:
  • Until ($U$): $\xi \models_k \varphi_1 U \varphi_2$ iff $\exists t \geq k$ s.t. $\xi \models_t \varphi_2$ and $\forall j \in [k, t-1]: \xi \models_j \varphi_1$
  • Release ($R$): $x \in \mathbb{R}^n$0 iff either $x \in \mathbb{R}^n$1 holds until $x \in \mathbb{R}^n$2 becomes true or $x \in \mathbb{R}^n$3 holds forever.
• Derived operators: "always" ($x \in \mathbb{R}^n$4) as $x \in \mathbb{R}^n$5, and "eventually" ($x \in \mathbb{R}^n$6) as $x \in \mathbb{R}^n$7.

RTL semantics are defined over possibly infinite system runs, with satisfaction determined inductively as above.

2. Discrete Task Planning: SAT Encodings of Temporal Logic

Synthesis begins by abstracting the continuous state space into discrete polytopic regions and constructing a Kripke-structure graph representing possible discrete transitions:

• State-space partition: $x \in \mathbb{R}^n$8, where each polytope $x \in \mathbb{R}^n$9 is labeled with a unique set of atomic predicates.
• Discrete abstraction: $$\psi ::= \pi \mid \lnot \pi \mid \psi_1 \land \psi_2 \mid \psi_1 \lor \psi_2$$0 with $$\psi ::= \pi \mid \lnot \pi \mid \psi_1 \land \psi_2 \mid \psi_1 \lor \psi_2$$1 discrete states (polytopes), $$\psi ::= \pi \mid \lnot \pi \mid \psi_1 \land \psi_2 \mid \psi_1 \lor \psi_2$$2 adjacency, $$\psi ::= \pi \mid \lnot \pi \mid \psi_1 \land \psi_2 \mid \psi_1 \lor \psi_2$$3 labeling.
• SAT encoding: For a planning horizon $$\psi ::= \pi \mid \lnot \pi \mid \psi_1 \land \psi_2 \mid \psi_1 \lor \psi_2$$4,
  • Variables: For each $$\psi ::= \pi \mid \lnot \pi \mid \psi_1 \land \psi_2 \mid \psi_1 \lor \psi_2$$5, $$\psi ::= \pi \mid \lnot \pi \mid \psi_1 \land \psi_2 \mid \psi_1 \lor \psi_2$$6 states, ($$\psi ::= \pi \mid \lnot \pi \mid \psi_1 \land \psi_2 \mid \psi_1 \lor \psi_2$$7 subformula truth flags, loop selectors $$\psi ::= \pi \mid \lnot \pi \mid \psi_1 \land \psi_2 \mid \psi_1 \lor \psi_2$$8 for recognizing cycles.
  • Formula structure:

  $$\psi ::= \pi \mid \lnot \pi \mid \psi_1 \land \psi_2 \mid \psi_1 \lor \psi_2$$9 - Temporal operators are reduced to local (one-step) constraints and "eventually" clauses ensure satisfaction over loops.

• Incremental SAT solving: $$\varphi ::= \psi \mid \lnot \psi \mid \varphi_1 \land \varphi_2 \mid \varphi_1 \lor \varphi_2 \mid \varphi_1 U \varphi_2 \mid \varphi_1 R \varphi_2$$0 is increased until either a satisfying assignment (feasible abstract trajectory) is found or $$\varphi ::= \psi \mid \lnot \psi \mid \varphi_1 \land \varphi_2 \mid \varphi_1 \lor \varphi_2 \mid \varphi_1 U \varphi_2 \mid \varphi_1 R \varphi_2$$1 exceeds the abstraction's recursive diameter, proving unrealizability.

3. Continuous Motion Planning: LP Synthesis and Counterexample Refinement

Given a candidate discrete plan (abstract state trace) from the SAT layer, continuous instantiation is attempted:

• Trajectory LP formulation:

  • For the state/control sequence $$\varphi ::= \psi \mid \lnot \psi \mid \varphi_1 \land \varphi_2 \mid \varphi_1 \lor \varphi_2 \mid \varphi_1 U \varphi_2 \mid \varphi_1 R \varphi_2$$2:
  • Dynamics enforced: $$\varphi ::= \psi \mid \lnot \psi \mid \varphi_1 \land \varphi_2 \mid \varphi_1 \lor \varphi_2 \mid \varphi_1 U \varphi_2 \mid \varphi_1 R \varphi_2$$3 within slack $$\varphi ::= \psi \mid \lnot \psi \mid \varphi_1 \land \varphi_2 \mid \varphi_1 \lor \varphi_2 \mid \varphi_1 U \varphi_2 \mid \varphi_1 R \varphi_2$$4.
  • Polytope membership: $$\varphi ::= \psi \mid \lnot \psi \mid \varphi_1 \land \varphi_2 \mid \varphi_1 \lor \varphi_2 \mid \varphi_1 U \varphi_2 \mid \varphi_1 R \varphi_2$$5 (polytope labeled by $$\varphi ::= \psi \mid \lnot \psi \mid \varphi_1 \land \varphi_2 \mid \varphi_1 \lor \varphi_2 \mid \varphi_1 U \varphi_2 \mid \varphi_1 R \varphi_2$$6).
• Feasibility check: If LP is feasible, a dynamically feasible trajectory $$\varphi ::= \psi \mid \lnot \psi \mid \varphi_1 \land \varphi_2 \mid \varphi_1 \lor \varphi_2 \mid \varphi_1 U \varphi_2 \mid \varphi_1 R \varphi_2$$7 satisfying the RTL formula is constructed.
• Infeasibility handling: If LP is infeasible, extract an Irreducibly Inconsistent Set (IIS) of polytope-membership constraints yielding a "minimal counterexample" discrete prefix. This counterexample is fed back as a "blocking clause" to the SAT layer, refining subsequent plans to avoid impossible behavior.

4. On-the-fly SAT–LP Iteration and Algorithmic Guarantees

The overall synthesis iterates in a Counterexample-Guided Inductive Synthesis (CEGIS) loop:

1. Initialize $$\varphi ::= \psi \mid \lnot \psi \mid \varphi_1 \land \varphi_2 \mid \varphi_1 \lor \varphi_2 \mid \varphi_1 U \varphi_2 \mid \varphi_1 R \varphi_2$$8, $$\varphi ::= \psi \mid \lnot \psi \mid \varphi_1 \land \varphi_2 \mid \varphi_1 \lor \varphi_2 \mid \varphi_1 U \varphi_2 \mid \varphi_1 R \varphi_2$$9.
2. While the unbounded SAT formula $U$0 is satisfiable:
   • Solve SAT for horizon $U$1, retrieve candidate discrete plan.
   • Invoke LP for continuous plan validation.
   • If LP feasible, return solution.
   • If LP infeasible, extract counterexample and add to $U$2, repeat.
3. If SAT for all $U$3 up to recursion diameter is unsatisfiable, report unrealizability.

Soundness: Any returned trajectory $U$4 satisfies the original RTL specification (discrete plan ensures logical soundness, LP enforces physical realizability).

Completeness: If a feasible trajectory exists, for some finite $U$5 and after a finite number of counterexample iterations, the procedure returns a correct solution. Formal arguments use (i) simulation of $U$6 by $U$7, (ii) bounded-diameter property ensuring any feasible run is discovered for some $U$8, (iii) refinement guarantees that only infeasible prefixes are discarded, and (iv) coverage of all possible $U$9.

5. Application Example: Double Integrator "Inspection Task"

A canonical instance demonstrates practical deployment:

• System: Planar double integrator, $\xi \models_k \varphi_1 U \varphi_2$0, $\xi \models_k \varphi_1 U \varphi_2$1.
• Predicates: Region $\xi \models_k \varphi_1 U \varphi_2$2 (unsafe), $\xi \models_k \varphi_1 U \varphi_2$3 (target), $\xi \models_k \varphi_1 U \varphi_2$4 (inspection waypoints).
• Specification:

$\xi \models_k \varphi_1 U \varphi_2$5

— "Always: before reaching $\xi \models_k \varphi_1 U \varphi_2$6 avoid $\xi \models_k \varphi_1 U \varphi_2$7, and before reaching $\xi \models_k \varphi_1 U \varphi_2$8 visit $\xi \models_k \varphi_1 U \varphi_2$9."

• Execution:

1. Abstract the plane into ~15 polytopes partitioning the $\exists t \geq k$0 space according to predicate constancy; build adjacency graph.
2. Incrementally increase SAT horizon. For $\exists t \geq k$1, a feasible plan found: chain of polytope indices forming a loop.
3. Decode as a discrete Kripke structure, and invoke LP for $\exists t \geq k$2.
4. LP yields a feasible, smooth trajectory visiting $\exists t \geq k$3, avoiding $\exists t \geq k$4, and looping to $\exists t \geq k$5.

This architecture enables formal enforcement of temporal orderings and reach–avoid constraints under full system dynamics, not just over discretized abstractions.

6. Scalability and Performance Results

Empirical results in (Silva et al., 2020) demonstrate:

• Feasibility/infeasibility decisions: On the inspection task, feasible cases resolved in $\exists t \geq k$6 ms, infeasible in $\exists t \geq k$7 ms, significantly outperforming abstraction-based quotients requiring $\exists t \geq k$8 s.
• Nonconvex maze: 2D maze planning in $\exists t \geq k$9 s (vs RRT's 20–30 s, MILP timeouts $\xi \models_t \varphi_2$0 s).
• High-dimensional systems: For an 18-state quadrotor, synthesis times range from $\xi \models_t \varphi_2$1 s to $\xi \models_t \varphi_2$2 s depending on environment, uniformly superior to SAT/SMT-based alternatives tested in the same setting.

The critical efficiency gain comes from strict separation: discrete, nonconvex temporal logic is handled with SAT; continuous, convex dynamics are verified by LP—combined on-the-fly, rather than via monolithic MILP or full precomputed abstraction.

7. Significance, Developments, and Outlook

Separation of temporal logic task planning into discrete and continuous subproblems, combined by CEGIS-style iteration, achieves a scalable and complete synthesis protocol for high-level robot planning. Unlike methods constrained to simple specifications, convex logic, or full discretization, this framework handles non-convex, unbounded RTL requirements in continuous state spaces with formal completeness guarantees.

This approach establishes a foundation for further developments in automatic controller synthesis from specification, including extensions to richer logic fragments, stochastic systems, and integration with data-driven or learning-based planning modules (Silva et al., 2020). It drives the transition from specification-centric design to correct-by-construction, verified autonomous systems in robotics and cyber-physical domains.