Stacked Cascode Transistors

• Stacked cascode transistors are series-connected FETs that combine TFT and HEMT devices to achieve high-voltage tolerance and rapid switching in integrated circuits.
• They employ precise 3D monolithic integration with careful thermal budget and alignment control to optimize performance metrics such as subthreshold slope and breakdown voltage.
• These devices are crucial for applications in power converters, level shifters, and RF amplifiers, enabling efficient solutions in electric vehicles and industrial power systems.

Stacked cascode transistors are series-connected field-effect devices arranged to combine the advantageous attributes of individual device technologies, achieving high breakdown voltage capability, enhanced switching behavior, and optimized interface control for advanced power, RF, and high-frequency integrated circuits. In the cascode configuration, two or more transistors are vertically stacked such that the upper device provides logic-level (normally-off) switching, and the lower device sustains high voltage swings, taking advantage of wide-bandgap or high-electron-mobility device physics. This architecture is central in applications demanding high voltage tolerance, fast switching, and integration-compatibility for next-generation power and RF systems.

1. Physical Architecture and Implementation

In reported 3D monolithic integrations, such as the amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) stacked on a gallium nitride (GaN) high electron mobility transistor (HEMT) substrate, the physical stack includes multiple epitaxial and dielectric layers grown and defined with precise process sequentiality. The structure comprises (from substrate upward): silicon, thick undoped GaN buffer (4.3 µm), GaN channel (300 nm), AlGaN barrier (26 nm), GaN cap (1 nm), in-situ SiN (2 nm), gate dielectrics, ohmic and gate metallization for the HEMT, passivation, then the TFT a-IGZO channel (either 30 nm or 10 nm), TFT metallization, and final passivation (Wu et al., 10 Jul 2025).

The equivalent-circuit arrangements connect a normally-off a-IGZO TFT (T₁) in series atop a normally-on GaN HEMT (T₂). In operation, logic-level input on T₁’s gate regulates the overall current, while the HEMT absorbs the bulk of applied drain-to-source voltage, enabling reliable high-voltage operation (breakdown >1900 V).

2. Device Operation and Electrical Characteristics

The cascode arrangement operates as follows: in the ON-state ($V_{G1} > V_{TH1}$), T₁ conducts and T₂’s inherently conductive 2DEG channel completes the stack. In the OFF-state ($V_{G1} < V_{TH1}$), T₁ is shut off, and any high drain voltage appears across T₂, which is pinched off by an appropriately biased gate. Experimentally, for Sample B (10 nm a-IGZO), measured threshold voltages are $V_{TH1} \approx +0.53\,\text{V}$ for T₁ and $V_{TH2} \approx -4.47\,\text{V}$ for T₂. Subthreshold swing is $SS \approx 90.3\,\text{mV/dec}$, and ON/OFF current ratio is approximately $10^7$ (Wu et al., 10 Jul 2025).

Breakdown voltage, determined as the voltage at which drain current in the OFF-state reaches $10^{-3}\,\text{A}$, exceeds 1900 V for Sample B at $L_{GD} = 12\,\mu\text{m}$. This matches or approaches standalone GaN HEMT benchmarks, despite the integration of the TFT in series.

Sample	a-IGZO Thickness	$V_{TH1}$ (TFT)	Subthr. Swing	$I_{ON}/I_{OFF}$	Breakdown Voltage ($V_{BD}$)
Sample A	30 nm	–0.3 V	>100 mV/dec	$10^6$	Not stated
Sample B	10 nm	+0.53 V	90.3 mV/dec	$10^7$	$\approx$1983 V

3. Fabrication and Integration Process

The monolithic 3D integration process is governed by a thermal budget constraint, dictated by the high-temperature (850 °C) rapid thermal anneal for GaN HEMT formation, after which all subsequent TFT process steps are maintained at ≤250 °C to avoid degrading underlying HEMT device characteristics. The sequence includes formation of the HEMT, deposition/passivation to isolate sensitive surfaces, deposition and patterning of the a-IGZO TFT atop the prepared substrate, and interface engineering with SiO₂ passivation to prevent inter-layer damage (Wu et al., 10 Jul 2025).

Key integration challenges include alignment precision to ensure vertical connectivity between TFT and HEMT, minimization of parasitic capacitance introduced by stacked metallization, and process isolation to prevent cross-contamination or drift-region degradation.

4. Design Considerations and Performance Optimization

Thin a-IGZO channels (10 nm vs. 30 nm) demonstrate improvements in device metrics: sharper subthreshold slopes, positive threshold voltages, reduced trap density, and lower leakage current. This enhances ON/OFF ratios and increases breakdown voltage—reflecting stronger gate control and more robust drift-region depletion. Sample B’s reduced channel thickness achieves superior electrical figures-of-merit, confirming the critical role of channel geometry/doping in stacked cascode efficacy.

Optimization of the drift region (L_GD) is necessary to balance ON-resistance versus breakdown capability. Additional interconnect capacitance from vertical integration must be minimized to maintain switching speed and efficiency.

5. Application Domains and System-Level Relevance

Integrated stacked cascode transistors enable compact, on-chip solutions for power converters, level shifters, and high-voltage switches—in particular for electric vehicle inverters and advanced industrial power systems. The demonstrated >1900 V total stack breakdown for monolithic 3D cascode devices supports the feasibility of deploying TFT logic control atop power-grade GaN HEMT layers, achieving functional integration unattainable by planar or discrete cascodes. This integration pathway enables scaling of high-voltage ICs for both logic and power domains.

6. Advantages, Limitations, and Future Prospects

Advantages include high-voltage tolerance in a reduced footprint, logical-level control afforded by TFTs, and minimized wire-bonded or off-chip interconnects, reducing parasitics and enhancing reliability. However, thermal budget constraints impose material and device choices for upper-layer devices, and process complexity introduces yield and uniformity challenges. The area and voltage-scaling advantages position these stacks for next-generation monolithic power ICs, contingent on continued advances in vertical process integration and wide-bandgap device engineering (Wu et al., 10 Jul 2025).

7. Context within Power and RF Device Innovation

While stacked cascode principles are utilized in both CMOS and III-V-based amplifier cores, such as Doherty PA topologies, detailed multi-device cascode stack implementations (N>2) and their analytical scaling remain relatively underreported in mainstream mm-wave PA literature. For example, while transformer-based Doherty PA designs reference use of stacked cascode transistors in their output-stage topology, explicit device-level implementation and scaling analysis are limited—highlighting a research frontier for further quantitative exploration (Wang et al., 15 Nov 2025). A plausible implication is the opportunity for cross-fertilization of integration concepts between monolithic 3D power devices and mm-wave/high-frequency CMOS/RF architectures.