Sporadic 3-Phase Tasks: Model and Analysis

• Sporadic 3-phase tasks are real-time tasks with three sequential phases—read, execution, and write—that manage both data loading and local computation.
• This model uses fixed-priority scheduling with preemption thresholds to harmonize CPU execution with serialized memory access on partitioned multicore platforms.
• Experimental results indicate that employing preemption thresholds can reduce required local memory by up to 2.5× compared to fully preemptive scheduling.

Searching arXiv for the cited papers and closely related work on sporadic 3-phase tasks. Sporadic 3-phase tasks are sporadically released real-time tasks whose jobs consist of three ordered phases: a read phase that loads all required input data and instructions from shared main memory into local memory, an execution phase that performs computation using only local memory, and a write phase that writes output data back to shared main memory. In the formulation studied for partitioned multicore systems, each task is represented by $$(T_i, D_i, M_i, P_i, \theta_i, C_i^r, C_i^e, C_i^w)$$, with $D_i \le T_i$, total worst-case execution time $C_i = C_i^r + C_i^e + C_i^w$, and utilization $u_i = \frac{C_i}{T_i}$. This model is motivated by phased execution on complex COTS multi-core platforms and by the need to manage both schedulability and local-memory occupancy under preemption (Thilakasiri et al., 27 Aug 2025).

1. Formal definition and execution semantics

A sporadic 3-phase task system is an application-level task set

$\tau=\{\tau_1,\tau_2,\dots,\tau_n\}.$

Each task $\tau_i$ is characterized by a minimum inter-arrival time $T_i$, a relative deadline $D_i$, a memory footprint $M_i$, a nominal fixed priority $P_i$, a preemption threshold $D_i \le T_i$0, and phase-specific WCETs $D_i \le T_i$1, $D_i \le T_i$2, and $D_i \le T_i$3. The constraint $D_i \le T_i$4 holds, and the model assumes constrained deadlines, i.e.,

$D_i \le T_i$5

A release of task $D_i \le T_i$6 is denoted $D_i \le T_i$7, the $D_i \le T_i$8-th job of that task (Thilakasiri et al., 27 Aug 2025).

The memory footprint is defined as

$D_i \le T_i$9

where $C_i = C_i^r + C_i^e + C_i^w$0 is code size, $C_i = C_i^r + C_i^e + C_i^w$1 is total data size, and $C_i = C_i^r + C_i^e + C_i^w$2 is maximum stack usage. This footprint is not merely descriptive: under keep-in-core preemption, it determines whether nested preemptions can be realized within the local memory of a core (Thilakasiri et al., 27 Aug 2025).

The phase semantics are fixed and explicit.

Phase	Function	Preemptive behavior
Read phase (R)	Loads required input data and instructions from shared main memory into local memory	Non-preemptive
Execution phase (E)	Performs computation using only local memory	Preemptive subject to preemption thresholds
Write phase (W)	Writes output data back from local memory to shared main memory	Non-preemptive

This is the standard PREM/AER-style semantics specialized to three phases: memory-load, local execution, and memory write-back. The formulation explicitly notes that the task set is not segmented; a task is treated as one 3-phase unit rather than multiple streamable segments (Thilakasiri et al., 27 Aug 2025).

2. Platform model, resource arbitration, and threshold semantics

The platform is a multicore system with $C_i = C_i^r + C_i^e + C_i^w$3 cores, denoted $C_i = C_i^r + C_i^e + C_i^w$4, where each core has a private local memory of size $C_i = C_i^r + C_i^e + C_i^w$5, and all cores access main memory through a shared interconnect. Tasks are statically assigned to cores, migration is not allowed, and local memory stores the code and data used during the execution phase. Main-memory access is serialized by scheduling memory phases so that only one memory phase is active at a time. The bus or interconnect always serves the highest-priority pending memory phase globally, and that memory phase executes non-preemptively to completion (Thilakasiri et al., 27 Aug 2025).

CPU scheduling is partitioned and fixed-priority. On each core, execution phases are scheduled by fixed priority with preemption thresholds, whereas memory phases are globally ordered by nominal priority rather than threshold. Threshold semantics are phase-aware: at the start of the read phase, the task’s active priority is raised from $C_i = C_i^r + C_i^e + C_i^w$6 to $C_i = C_i^r + C_i^e + C_i^w$7, and this elevated threshold remains in effect through the read phase, the execution phase, and until the end of the write phase, after which the priority is restored to its nominal value. However, this only affects local-core CPU preemption; global scheduling of memory phases on the bus still uses nominal priorities (Thilakasiri et al., 27 Aug 2025).

A task $C_i = C_i^r + C_i^e + C_i^w$8 can be preempted only during its execution phase. Once its threshold is active, any job on the same core with nominal priority

$C_i = C_i^r + C_i^e + C_i^w$9

may preempt $u_i = \frac{C_i}{T_i}$0’s execution phase, whereas jobs with

$u_i = \frac{C_i}{T_i}$1

cannot do so. Tasks on other cores cannot preempt its CPU execution, but they can interfere with its read and write phases through shared-bus contention (Thilakasiri et al., 27 Aug 2025).

The response-time analysis classifies tasks relative to $u_i = \frac{C_i}{T_i}$2 into six categories: $u_i = \frac{C_i}{T_i}$3

$u_i = \frac{C_i}{T_i}$4

$u_i = \frac{C_i}{T_i}$5

$u_i = \frac{C_i}{T_i}$6

$u_i = \frac{C_i}{T_i}$7

$u_i = \frac{C_i}{T_i}$8

The purpose of this classification is to distinguish the delay mechanisms before a job starts its read phase from those that remain possible after the threshold has been raised. Before $u_i = \frac{C_i}{T_i}$9 starts, tasks with higher or equal nominal priority can delay it; after the read phase starts and the threshold is active, only category $\tau=\{\tau_1,\tau_2,\dots,\tau_n\}.$0 tasks can actually preempt its execution (Thilakasiri et al., 27 Aug 2025).

3. Worst-case response-time analysis

The response-time analysis for sporadic 3-phase tasks under partitioned fixed-priority scheduling with preemption thresholds is a sufficient worst-case analysis that combines local CPU effects with global memory-bus effects. It is built around the longest level-$\tau=\{\tau_1,\tau_2,\dots,\tau_n\}.$1 active period. The paper defines the level-$\tau=\{\tau_1,\tau_2,\dots,\tau_n\}.$2 pending load $\tau=\{\tau_1,\tau_2,\dots,\tau_n\}.$3 as the amount of processing still pending at time $\tau=\{\tau_1,\tau_2,\dots,\tau_n\}.$4 due to jobs with priority higher than or equal to $\tau=\{\tau_1,\tau_2,\dots,\tau_n\}.$5 released strictly before $\tau=\{\tau_1,\tau_2,\dots,\tau_n\}.$6, and the level-$\tau=\{\tau_1,\tau_2,\dots,\tau_n\}.$7 active period $\tau=\{\tau_1,\tau_2,\dots,\tau_n\}.$8 as an interval $\tau=\{\tau_1,\tau_2,\dots,\tau_n\}.$9 such that $\tau_i$0 for all $\tau_i$1 and $\tau_i$2. Because limited preemption causes the self-pushing phenomenon, the worst-case response time may occur not for the first job in the active period but for a later one, so all jobs in the active period are analyzed (Thilakasiri et al., 27 Aug 2025).

The analysis decomposes delay into four terms: intra-core interference $\tau_i$3, intra-core blocking $\tau_i$4, inter-core interference $\tau_i$5, and inter-core blocking $\tau_i$6. For a task $\tau_i$7 assigned to core $\tau_i$8, intra-core interference is

$\tau_i$9

with the standard sporadic release bound

$T_i$0

Inter-core interference is

$T_i$1

The number of suffered remote-memory blockings is bounded by

$T_i$2

and the number of caused blockings by lower-priority remote tasks is

$T_i$3

These quantities reflect that each local execution phase may be followed by read and write phases, and each remote job can contribute at most two blocking opportunities through its own read and write phases (Thilakasiri et al., 27 Aug 2025).

The local blocking term is the point where 3-phase semantics and thresholds interact most strongly. The paper states that a category-$T_i$4 lower-priority task can block $T_i$5 only by one non-preemptive memory phase, whereas a category-$T_i$6 or $T_i$7 task may block for its entire job execution $T_i$8, because once it starts and raises its own priority to $T_i$9, $D_i$0 cannot preempt it if $D_i$1. Only one such lower-priority local blocking can occur in a level-$D_i$2 active period (Thilakasiri et al., 27 Aug 2025).

The longest active period on core $D_i$3 is the first positive fixed point of

$D_i$4

with

$D_i$5

The number of jobs of $D_i$6 in the active period is therefore

$D_i$7

For the $D_i$8-th job, the start time of the read phase, measured from the start of the active period, is the first positive fixed point of

$D_i$9

To capture self-pushing, the count of releases in this start-time recurrence uses

$M_i$0

The finish time of the write phase is then

$M_i$1

A key refinement is that once the read phase has started and the threshold has been raised, only category $M_i$2 tasks are considered as local interfering tasks in the interval from $M_i$3 to $M_i$4. The final worst-case response time is

$M_i$5

and the task is schedulable if

$M_i$6

This analysis differs from ordinary sporadic-task analysis because it must model separate CPU and memory resources, globally serialized and non-preemptive memory phases, and the distinction between interference before read-start and interference after threshold activation (Thilakasiri et al., 27 Aug 2025).

4. Local-memory feasibility and preemption-threshold assignment

The memory analysis is specific to the keep-in-core realization of preemption. When a task is preempted during its execution phase, its loaded code, data, and intermediate local state remain resident in local memory; the preempting task’s code and data are loaded above it, stack-like. If nested preemptions occur, all tasks in the chain remain resident simultaneously. Consequently, the worst-case local-memory requirement on a core is the largest sum of $M_i$7 over any feasible preemption chain on that core (Thilakasiri et al., 27 Aug 2025).

A preemption chain starting from base task $M_i$8 is

$M_i$9

where $P_i$0 is the set of tasks mapped to core $P_i$1, and $P_i$2 denotes the task at position $P_i$3 in the chain. A chain is valid if each consecutive task can preempt the previous one; the stated constraint is

$P_i$4

The optimization objective is

$P_i$5

The task set is memory-feasible iff, for every core and every task assigned to that core,

$P_i$6

The comparison among non-preemptive, fully preemptive, and threshold-based execution follows directly from this formulation. In the non-preemptive case, no task can be preempted during execution, so every chain has length $P_i$7. In the fully preemptive case, $P_i$8 for all tasks, so any higher-priority local task may preempt, and chains can become long. In the preemption-threshold case, raising $P_i$9 removes some preemption edges from the local preemption graph, shortens feasible chains, and reduces the maximum cumulative resident memory (Thilakasiri et al., 27 Aug 2025).

Threshold assignment is based on the Maximal Preemption Threshold Assignment Algorithm (MPTAA). The procedure starts from fully preemptive thresholds,

$D_i \le T_i$00

then increases thresholds one level at a time while preserving schedulability. The adaptation to the multicore 3-phase setting relies on the fact that a unit increment of $D_i \le T_i$01 affects only the local task $D_i \le T_i$02 with

$D_i \le T_i$03

that lies in category $D_i \le T_i$04. Because thresholds only affect local-core preemption relations and do not affect remote cores or bus arbitration, only that single task needs to be rechecked after each increment. This enables a practical synthesis loop: partition tasks to cores, assign nominal priorities, initialize fully preemptive thresholds, check schedulability by the response-time analysis, increment thresholds from higher to lower priority, revert increments that make the newly affected task unschedulable, and then verify memory-feasibility through preemption chains (Thilakasiri et al., 27 Aug 2025).

5. Experimental characterization

The evaluation compares three execution-phase policies: non-preemptive execution phases (NP), fully preemptive execution phases (FP), and limited preemption using thresholds (PT). The default experimental parameters are total utilization $D_i \le T_i$05, $D_i \le T_i$06 cores, local memory $D_i \le T_i$07, and $D_i \le T_i$08 tasks. Priorities are unique and assigned by rate-monotonic policy, partitioning uses worst-fit mapping, and timing parameters are assumed to be non-negative integers (Thilakasiri et al., 27 Aug 2025).

Two task-set families are used. One uses automotive periods

$D_i \le T_i$09

with probabilities

$D_i \le T_i$10

The other uses log-uniform minimum inter-arrival times in $D_i \le T_i$11 ms. Utilizations are generated with Dirichlet-Rescale for a target total $D_i \le T_i$12, then

$D_i \le T_i$13

The number of labels per task $D_i \le T_i$14 is uniform in $D_i \le T_i$15, $D_i \le T_i$16 is uniform in $D_i \le T_i$17, and $D_i \le T_i$18 is uniform in $D_i \le T_i$19. The ratio of total memory-phase time to total execution time is

$D_i \le T_i$20

the ratio between read and write time is

$D_i \le T_i$21

and phase times are generated from

$D_i \le T_i$22

$D_i \le T_i$23

$D_i \le T_i$24

$D_i \le T_i$25

Task sets are filtered to exclude trivially unschedulable cases in which a low-priority task has a memory phase longer than a higher-priority task’s minimum inter-arrival time (Thilakasiri et al., 27 Aug 2025).

When local memory size $D_i \le T_i$26 varies from 16 KB to 112 KB in 8 KB steps, FP has 37% more schedulable task sets than NP. PT preserves the schedulability of FP because MPTAA starts from an FP-schedulable system and only keeps threshold increases that preserve schedulability. Memory feasibility of FP is poor at small $D_i \le T_i$27: zero until 72 KB. FP needs 104 KB local memory to achieve 100% memory feasibility for all schedulable task sets, whereas PT achieves the same at 40 KB, a $D_i \le T_i$28 reduction in required local memory. PT yields up to 40% more task sets than FP that are both schedulable and memory-feasible (Thilakasiri et al., 27 Aug 2025).

When the core count $D_i \le T_i$29 varies from 2 to 34, schedulability improves with more cores. For combined schedulability and memory-feasibility, FP needs 16 cores to achieve 100% memory-feasible acceptance for all schedulable task sets, while PT needs only 8 cores. When total utilization $D_i \le T_i$30 varies from 0.1 to 3.4 in steps of 0.3, schedulability decreases for all methods, but PT consistently improves memory-feasibility relative to FP for both automotive-period and log-uniform task sets. The paper summarizes this trade-off by stating that preemption thresholds can significantly reduce the memory usage by $D_i \le T_i$31 compared to fully preemptive scheduling, while maintaining high schedulability ratios $D_i \le T_i$32 compared to non-preemptive scheduling (Thilakasiri et al., 27 Aug 2025).

6. Relation to adjacent real-time task models

Sporadic 3-phase tasks sit at the intersection of phased execution, partitioned multiprocessor scheduling, and memory-sensitive preemption control, but they should not be conflated with either rate-based parallel-task models or the classic single-segment sporadic model. In particular, the model in "Integrating Job Parallelism in Real-Time Scheduling Theory" (0805.3237) allows a single job to execute on several processors at the same time and is best understood as a continuous-rate malleable-job model rather than a segmented precedence model. It can approximate a 3-phase task only if one collapses all phases into a single speedup tuple $D_i \le T_i$33 and ignores internal precedences and segment boundaries. It cannot model a first sequential phase that must finish before a parallel middle phase starts, a final sequential phase after the parallel section, arbitrary phase ordering constraints, release jitter induced by self-suspension, different speedup functions in different phases, or DAG nodes with critical paths. A plausible implication is that rate-based malleable parallelism and true 3-phase structure answer different questions: the former abstracts aggregate processor demand, whereas the latter retains explicit memory and execution phase semantics (0805.3237).

The classic partitioned packing model in "Packing Sporadic Real-Time Tasks on Identical Multiprocessor Systems" (Chen et al., 2018) also does not explicitly study sporadic 3-phase tasks. It assumes independent sporadic tasks $D_i \le T_i$34, each job contributing a single execution demand $D_i \le T_i$35, and uses partitioned scheduling with preemptive EDF on identical multiprocessors. Its processor-minimization results, transformed-task bin-packing framework, and demand-bound reasoning are therefore baseline theory rather than a direct schedulability theory for 3-phase tasks. The direct applicability stops at the point where a model needs to account for multiple ordered phases, non-CPU suspension or communication phases, and internal precedence constraints (Chen et al., 2018).

The broader feasibility-theoretic background comes from "Feasibility Analysis of Sporadic Real-Time Multiprocessor Task Systems" (Bonifaci et al., 2010), which studies classical sporadic constrained-deadline task systems on identical multiprocessors with preemption and migration allowed. That work distinguishes feasibility, online feasibility, and schedulability; models adversarial releases by finite graph and game constructions; and proves that discrete-time schedules are as powerful as continuous-time schedules for the classical sporadic model. For sporadic 3-phase tasks, this is foundational background on adversarial release modeling and on the difference between clairvoyant feasibility and online schedulability, but it is not a direct model of read, execution, and write phases. This suggests that extending exact feasibility analysis to 3-phase tasks would require richer local task state, explicit eligibility conditions for phase execution, and new proofs for any discrete-time reduction (Bonifaci et al., 2010).

Within that landscape, sporadic 3-phase tasks are most precisely characterized as a phased real-time model in which each job alternates between globally serialized memory access and local-memory-only computation, and in which limited preemption is attractive because it mediates between the blocking of non-preemptive execution and the local-memory blow-up of full preemption. The current state of the art represented here is therefore not a generic sporadic-task theory with minor adjustments, but a dedicated analysis framework whose distinctive objects are 3-phase jobs, globally serialized memory phases, threshold-controlled execution preemption, and preemption-chain-based local-memory feasibility (Thilakasiri et al., 27 Aug 2025).